MPF0900AMBA2ES datasheet(81/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

System requirements must be taken into account when selecting the pullup voltage and resistance. To prevent

the output from being pulled high in the ULPOFF state, the selection must ensure that the pullup voltage is not

present during off condtions.

When the output is set as a push-pull driver, the PF09 will use the VIN internally to set the high state on the

GPIO4 pin.

The GPIO4 uses the OTP_SEQ_TBASE[1:0] and the OTP_GPO4_SEQ[7:0] bits, to enable the GPO by default

at a specific time slot during the power-up sequence. Refer to section 16.3.3 Regulator Power-up Sequence, for

a detailed description of the Power up sequence.

The GPIO4 pin is designed to have independent control configuration during the RUN and the STANDBY states,

to allow full control of the GPIO4 when going in and out of the STANDBY state.

In the RUN state, the level of the GPIO4 pin can be controlled manually via the GPIO4_RUN bit.

GPIO4_RUN

GPIO4 state

Low

High

Table 97. GPIO4 state in RUN

In the STANDBY state, the level of the GPIO4 pin can be controlled manually via the GPIO4_STBY bit.

GPIO4_STBY

GPIO4 state

Low

High

Table 98. GPIO4 state in STANDBY

12.8.13 XFAILB

XFAILB is a bidirectional pin with an open-drain output. The XFAILB is able to accept a pullup voltage from 1.4

V to 5.5 V, typically pulled up to VANA in order to reduce current consumption during the Low-power off state.

Additionally, a 100 nF capacitor is recommended to improve the EMC performance.

The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

OTP_XFAILB_EN

XFAIL operation

Disabled

Enabled

Table 99. XFAIL operation

When the XFAILB mode is disabled, a transition on the XFAILB pin is ignored during the power-up or SYSTEM

ON states. Because of this, no synchronization is possible.

When the XFAILB mode is enabled, the XFAILB pin is used to synchronize two or more PMICs during power-up

and power-down events.

12.8.13.1 Power-up synchronization

During the OFF states, the XFAILB pin is asserted low internally. It will remain asserted during the PWRON

event until it is ready to start the power-up sequence. Once the device meets all the conditions to start the

power-up sequence, the XFAILB is released internally.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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