MPF0900AMBA2ES datasheet(154/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

• The device is powered down into any of the OFF states

• The device moves into the DFS state

• The XFAILB pin is asserted externally

• A dynamic CRC (DCRC) fault is present

• A VIN_OV condition is present

• An XRESET event is present

• An OV/UV/ILIM condition is present and the fault is not bypassed

• An FCCU failure is detected

• An ERRMON failure is detected

• The BGMON detects a bandgap drift condition

• The CLKMN detects a clock drift condition

• A short condition is detected on PGOOD or FS0B outputs

During the RUN states, every time the FS0B pin is asserted the MCU must perform the necessary diagnostic

to clear all fault conditions and request an FS0B release command, to release the pin and resume normal

operation.

14.5.1 FS0B pin diagnostic bit

The FS0B_S bit provides the real-time state of the FS0B pin.

FS0B_S

FS0B status

Pin sensed LOW

Pin sensed HIGH

Table 199. FS0B status bit

The FS0B_FLT_I interrupt is provided to notify the system of a short-to-high or short-to-low condition on the

FS0B pin. The FS0B fault event will assert the INTB pin if the FS0B_FLT_I interrupt is not masked.

The MCU can inspect the specific condition causing the FS0B_FLT_I interrupt to assert by reading the real-time

sense bits FS0B_S2H (short to high) and FS0B_S2L (short to low).

When the FS0B pin is being driven LOW internally, and the FS0B_S bit is sensing a HIGH state, the FS0B_S2H

bit is set HIGH until the condition is no longer present.

When the FS0B pin is released HIGH internally, and the FS0B_S is sensing a LOW state, the FS0B_S2L bit is

set HIGH until the condition is no longer present.

Note: Bits with _S in the names are sense bits, which are real time. Their values may disappear after the

condition in question goes away. Bits with _I in their names may be called flags or interrupt bits. These are

sticky bits, and their values will remain after the event is over.

14.5.2 Redundant FS0B control

The FS0B pin is provided with redundant control logic to ensure the pin is able to enter the safe state during

critical fault conditions (aside from the standard monitoring mechanism), including the loss of the main control

input supply (VIN), loss or misbehavior of the internal logic supply (VDIG), and the loss or misbehavior of

internal clocks.

In devices targeting high safety integrity levels featuring the digital machine supervisor (DMS) block, secondary

control for the FS0B pin is provided by the DMS circuit to support FS0B assertion on fault conditions generated

due to a misbehavior or inoperation of the main logic controller.

The third level of redundancy for the FS0B is achieved with an analog path to ensure the pin is asserted LOW

if none of the primary control paths are available. The analog path is intended to provide hard control of the

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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