MPF0900AMBA2ES datasheet(54/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

If the OV/UV fault is acknowledged before the fault timer is expired, the fault timer is stopped and the system

will resume normal operation until a new OV/UV condition is detected.

If the OV/UV fault is not acknowledged before the fault timer expires, the PMIC will generate a hard fault and

start a full power-down sequence, including the VAON regulator at the end of the power-down sequence. The

power-down delay will be applied after the VAON is disabled, to allow the VAON output to be discharged.

Once the power-down sequence is finished, the device will proceed to the Fail-safe transition and the VAON

supply will be re-enabled as soon as the state machine enters the LPOFF state.

When the VAON is operating in Reset mode, the VAON_OV_BYP and the VAON_UV_BYP bits are used to

bypass the protective reaction of the OV/UV condition, however the PF09 will still generate the corresponding

interrupt event to allow the system to track the fault conditions with a lower priority.

In Reset mode, the following VAON configuration bits have no effect on the fault management strategy for the

VAON regulator.

• VAON_FLT_REN

• VAON_OV_STATE

• VAON_UV_STATE

The table below summarizes the fault management strategy for the VAON supply in Always-on node.

State

Fault mode

(OTP_VAON_FMODE)

Fault reaction

OFF states

Don’t care

An UV condition in the VAON supply crossing the VAON_LP_UV

threshold will generate a self-reset of its output.

OTP_VAON_FMODE = 0

OV/UV interrupt is generated

PGOOD Asserted.

Fault counter increased.

Global fault timer started.

RUN state and

monitored STANDBY

OTP_VAON_FMODE = 1

OV/UV Interrupt is generated

PGOOD asserted.

Fault counter increased.

VAON fault timer started.

MCU must acknowledge and clear OV/UV flags.

If fault condition is cleared, return to normal operation

If fault condition is not cleared, hard fault includes VAON.

OTP_VAON_FMODE = 0 UV/OV conditions are ignored.

Low-power STANDBY

OTP_VAON_FMODE = 1 An UV crossing the VAON_LP_UV threshold will generate a full

PMIC power down (including the VAON)

Table 53. VAON always-on fault management strategy

12.6.3.2 VAON as system regulator

When VAON is configured as a system regulator, the OTP_VAON_FMODE bit has no effect on the reaction

when an OV/UV fault is detected in the VAON supply.

In order to allow the lowest power consumption during the low-power STANDBY state, the OV/UV monitoring

circuits are disabled, therefore the PF09 will not detect any OV/UV condition in the VAON output.

During the SYSTEM ON states (RUN and Monitored STANDBY states), the PF09 will react to an OV/UV

following the same rules as defined in in the fault management for system regulators:

• OV/UV interrupt flag is set and INTB pin asserted if the interrupt is not masked.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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