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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPF0900AMBA2ES датащи(PDF) 61 Page - NXP Semiconductors |
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MPF0900AMBA2ES датащи(HTML) 61 Page - NXP Semiconductors |
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61 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring Register BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SYSTEM INT EWARN_I GPIO_I OV_I UV_I ILIM_I MODE_I STATUS2_I STATUS1_I STATUS1 INT SDWN_I FREQ_RDY_I DCRC_I I2C_CRC_I PWRUP_I PWRDN_I FSYNC_FLT_I VIN_OV_I STATUS1 MSK SDWN_M FREQ_RDY_M DCRC_M I2C_CRC_M PWRUP_M PWRDN_M FSYNC_FLT_M VIN_OV_M STATUS1 SNS – – – – – – FSYNC_FLT_S VIN_OV_S STATUS2 INT VANA_OV_I VDIG_OV_I BGMON_I CLKMON_I THERM_155_I THERM_140_I THERM_125_I THERM_110_I STATUS2 MSK VANA_OV_M VDIG_OV_M BGMON_M CLKMON_M THERM_155_M THERM_140_M THERM_125_M THERM_110_M STATUS2 SNS VANA_OV_S VDIG_OV_S BGMON_S CLKMON_S THERM_155_S THERM_140_S THERM_125_S THERM_110_S STATUS3 INT – – LDO1EN_I VSELECT_I WD_ERROR_I BAD_CMD_I LBIST_DONE_I SHS_I STATUS3 MSK – – LDO1EN_M VSELECT_M WD_ERROR_M BAD_CMD_M LBIST_DONE_M SHS_M SW MODE INT DVSMAX_I DVSMIN_I - SW5_MODE_I SW4_MODE_I SW3_MODE_I SW2_MODE_I SW1_MODE_I SW MODE MSK DVSMAX_M DVSMIN_M - SW5_MODE_M SW4_MODE_M SW3_MODE_M SW2_MODE_M SW1_MODE_M SW ILIM INT SW1LS_OCP_I – – SW5_IL_I SW4_IL_I SW3_IL_I SW2_IL_I SW1_IL_I SW ILIM MSK SW1LS_OCP_M – – SW5_IL_M SW4_IL_M SW3_IL_M SW2_IL_M SW1_IL_M SW ILIM SNS – – – SW5_IL_S SW4_IL_S SW3_IL_S SW2_IL_S SW1_IL_S LDO ILIM INT – – – – – LDO3_IL_I LDO2_IL_I LDO1_IL_I LDO ILIM MSK – – – – – LDO3_IL_M LDO2_IL_M LDO1_IL_M LDO ILIM SNS – – – – – LDO3_IL_S LDO2_IL_S LDO1_IL_S SW UV INT MON2_UV_I MON1_UV_I – SW5_UV_I SW4_UV_I SW3_UV_I SW2_UV_I SW1_UV_I SW UV MSK MON2_UV_M MON1_UV_M – SW5_UV_M SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M SW UV SNS MON2_UV_S MON1_UV_S – SW5_UV_S SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S SW OV INT MON2_OV_I MON1_OV_I – SW5_OV_I SW4_OV_I SW3_OV_I SW2_OV_I SW1_OV_I SW OV MSK MON2_OV_M MON1_OV_M – SW5_OV_M SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M SW OV SNS MON2_OV_S MON1_OV_S – SW5_OV_S SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S LDO UV INT – – – – VAON_UV_I LDO3_UV_I LDO2_UV_I LDO1_UV_I LDO UV MSK – – – – VAON_UV_M LDO3_UV_M LDO2_UV_M LDO1_UV_M LDO UV SNS – – – – VAON_UV_S LDO3_UV_S LDO2_UV_S LDO1_UV_S LDO OV INT – – – – VAON_OV_I LDO3_OV_I LDO2_OV_I LDO1_OV_I LDO OV MSK – – – – VAON_OV_M LDO3_OV_M LDO2_OV_M LDO1_OV_M LDO OV SNS – – – – VAON_OV_S LDO3_OV_S LDO2_OV_S LDO1_OV_S PWRON INT – – – PWRON_8S_I PWRON_4S_I PWRON_3S_I PWRON_2S_I PWRON_1S_I PWRON MSK – – – PWRON_8S_M PWRON_4S_M PWRON_3S_M PWRON_2S_M PWRON_1S_M IO INT – – ERRMON_I FCCU1_I FCCU0_I PGOOD_FLT_I FS0B_FLT_I RSTB_FLT_I IO MSK – – ERRMON_M FCCU1_M FCCU0_M PGOOD_FLT_M FS0B_FLT_M RSTB_FLT_M IO SNS – GPIO4_S GPIO3_S FCCU1_S FCCU0_S PGOOD_S FS0B_S RSTB_S SHORT SNS GPIO2_S GPIO1_S FS0B_S2H FS0B_S2L PGOOD_S2H PGOOD_S2L RSTB_S2H RSTB_S2L Table 60. Interrupt register set I/O pins are provided with a sense bit to allow the system to monitor the real-time status of the pin. An I/O sense bit equal to 0 means the pin is physically sensed low, and a sense bit equal to 1 means the pin is physically sensed high. I/O pin Sense bit RSTB RSTB_S FS0B FS0B_S PGOOD PGOOD_S GPIO1 GPIO1_S GPIO2 GPIO2_S GPIO3 GPIO3_S Table 61. I/O pin sense bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 61 / 205 |
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