ADP1053ACPZ-R7 datasheet(24/84 Pages) AD

24 / 84 page

ADP1053

Data Sheet

Rev. A | Page 24 of 84

Digital Filters During Soft Start

A dedicated filter is used during soft start. The filter is disabled

at the end of the soft start routine, after which the voltage loop

digital filter is used. The soft start filter gain is programmable

using Bits[1:0] of Register 0xFE3E and Register 0xFE3F.

The soft start filter is used during the reference ramp time until

the high frequency ADCs of VS_A/VS_B are settled. The user

can program a debounce time for detecting the settling of the

high frequency ADC using Bits[5:4] of Register 0xFE3E and

with Bit 5. During the time that the soft start filter is used, the

SOFTSTART_FILTER_x flag is set.

SYNCHRONOUS RECTIFIER (SR) SOFT START

The turning on of the synchronous rectification (SR) signals

(OUT3, OUT4, OUT7, and OUT8) during a soft start can be

programmed in two ways. The SR signals can either be turned

on to their full PWM values immediately, or they can be turned

on in a soft start fashion, which ensures a smooth output ramp

during the soft start.

SR soft start changes the rising edge of the PWM output. Note

that the falling edge of an SR PWM output should not be modu-

lated. When turned on in a soft start, the rising edge of the SR

PWM output starts at the same instant as the falling edge, which

means a zero duty cycle. The rising edge moves left in a step of

40 ns per 1, 4, 16, or 64 switching cycles (programmable using

zero duty cycle to the desired duty cycle. When the rising edge

reaches 0, it wraps to restart at the end of the switching cycle.

When the ADP1053 is programmed to use SR during soft start,

the falling edge of SR outputs must be set to a lower value than

the rising edge of the following PWM output.

VOLT-SECOND BALANCE AND CURRENT BALANCE

The ADP1053 has two dedicated circuits to maintain current

balance/volt-second balance. To configure a PWM output

for volt-second balance or current balance, program Bit 4

in the appropriate PWM output setting register. (The PWM

output setting registers are Register 0xFE43, Register 0xFE47,

0xFE57, Register 0xFE5B, and Register 0xFE5F.) Volt-second

balance control can be disabled during soft start using Bit 3

of Register 0xFE08.

The balance control gains are programmable in Register 0xFE72.

The maximum modulation limit on the duty cycles is program-

mable at 80 ns and 160 ns using Bit 6 of Register 0xFE72.

When OUT1, OUT2, OUT3, and OUT4 are used for balance

control, the user can enable or disable the rising and falling

edges using Register 0xFE62 and Register 0xFE63. The

direction of the modulation is also programmable.

When OUT5, OUT6, OUT7, and OUT8 are used for balance

control, the user can enable or disable the rising and falling

edges using Register 0xFE64. The modulation direction is fixed.

When OUT5 and OUT7 are used and edge modulation for

balance control is enabled, increasing the balance control

modulation moves the edge to the right. For OUT6 and OUT8,

increasing the balance control modulation moves the edge to

the left.

Volt-Second Balancing (Based on CS Pin Signal)

Volt-second balance control is based on the sensed signal at

the CS pin following the rising edge of the OUT1 and OUT2

signals. When enabled, volt-second balance control makes the

programmed adjustment to the enabled PWM edges. This

feature can be effectively used in full-bridge applications,

eliminating the need for a dc blocking capacitor. The circuit

monitors the dc current flowing in both halves of the full bridge,

stores this information, and compensates the PWM drive signals

to ensure equal current flow in both halves of the full bridge.

The time required for the circuit to operate effectively can be

programmed and is typically in the range of 100 ms. Therefore,

during a transient condition, the volt-second balance relies on

the overcurrent condition to limit the PWM duty cycle.

Volt-second balance control uses the CS signal; it can be assigned

to Channel A or Channel C using Bit 7 of Register 0xFE72. When

volt-second balance control is used, OUT1 and OUT2 must be

assigned to the appropriate channel (Channel A or Channel C)

because the balance control circuit looks only for the rising edges

of OUT1 and OUT2 to start the balance control integration.

When the CS signal in the half cycle after the rising edge of

OUT1 is higher than the signal in the half cycle after the rising

edge of OUT2, the modulation value increases. The PWM

output edges move according to the values programmed in

Leading edge blanking functions can also be used at the sensed

CS signals for more accurate control results. The blanking time

follows the CS OCP blanking time. For more information, see

the Overcurrent Protection (OCP) Flags section.

Current Balancing (Based on CS1/CS2 Pin Signals)

Current balancing with regulated feedback is designed for oper-

ation in dual-phase, single-output topologies. Current balancing

is implemented to control the balance between CS1_A and CS1_B

or between CS2_A and CS2_B (use Bit 3 of Register 0xFE72 to

select CS1_A/CS1_B or CS2_A/CS2_B).

For dual-phase current balance control, when the CS1_A or CS2_A

value is larger than the CS1_B or CS2_B value, the modulation

value increases. The actions for different PWM output edges are

programmable using Register 0xFE62, Register 0xFE63, and

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