ADP1053ACPZ-R7 datasheet(75/84 Pages) AD

75 / 84 page

Data Sheet

ADP1053

Rev. A | Page 75 of 84

Table 115. Register 0xFE7A—Channel B PSON Setting

Bits

Bit Name

R/W

Description

PSON_B polarity

R/W

Setting this bit inverts the polarity of the PSON_B pin signal when hardware PSON_B is used.

0 = normal mode. A high signal on the PSON_B pin turns on Channel B.

1 = inverted. A low signal on the PSON_B pin turns on Channel B.

Software PSON_B

R/W

When software PSON_B is used, setting this bit turns on Channel B.

These bits specify which signal or signals are used as the PSON_B control.

Bit 5

Bit 4

PSON_B Control Selection

Always on. Channel B is always on.

Hardware PSON_B. The PSON_B pin turns Channel B on and off.

Software PSON_B. Bit 6 turns Channel B on and off.

[5:4]

PSON_B control

hardware/software

selection

R/W

Software and hardware PSON_B. Both the PSON_B pin and Bit 6 must be set

to turn on Channel B.

These bits specify the delay from when the PSON_B signal is set to when the soft start of Channel B begins.

Bit 3

Bit 2

Typical Delay Time

0 ms

50 ms

250 ms

[3:2]

PSON_B delay

R/W

1 sec

These bits specify the delay from when the PSON_B signal is cleared to when Channel B is turned off.

Bit 1

Bit 0

Typical Delay Time

0 ms

50 ms

250 ms

[1:0]

PSOFF_B delay

R/W

1 sec

Table 116. Register 0xFE7B—Additional Flag Reenable Delay and Channel C PSON Setting

Bits

Bit Name

R/W

Description

Channel C

additional flag

reenable delay

R/W

This bit specifies whether an additional PSON_C delay is added to the reenable delay after a flag is

cleared and before Channel C begins a soft start.

0 = no additional delay is added to the reenable delay.

1 = additional PSON_C delay is added to the reenable delay.

Channel B

additional flag

reenable delay

R/W

This bit specifies whether an additional PSON_B delay is added to the reenable delay after a flag is

cleared and before Channel B begins a soft start.

0 = no additional delay is added to the reenable delay.

1 = additional PSON_B delay is added to the reenable delay.

Channel A

additional flag

reenable delay

R/W

This bit specifies whether an additional PSON_A delay is added to the reenable delay after a flag is

cleared and before Channel A begins a soft start.

0 = no additional delay is added to the reenable delay.

1 = additional PSON_A delay is added to the reenable delay.

PSON_C control

selection

R/W

0 = Channel C is always on.

1 = Either PSON_A or PSON_B must be set to turn on Channel C.

These bits specify the delay from when the PSON_C signal is set to when the soft start of Channel C begins.

Bit 3

Bit 2

Typical Delay Time

0 ms

50 ms

250 ms

[3:2]

PSON_C delay

R/W

1 sec

These bits specify the delay from when the PSON_C signal is cleared to when Channel C is turned off.

Bit 1

Bit 0

Typical Delay Time

0 ms

50 ms

250 ms

[1:0]

PSOFF_C delay

R/W

1 sec

ADP1053ACPZ-R7 датащи(PDF) 75 Page - Analog Devices

ADP1053ACPZ-R7 датащи(HTML) 75 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL