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ADP1053ACPZ-R7 датащи(PDF) 80 Page - Analog Devices |
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ADP1053ACPZ-R7 датащи(HTML) 80 Page - Analog Devices |
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80 / 84 page ![]() ADP1053 Data Sheet Rev. A | Page 80 of 84 Table 131. Register 0xFEC1—Flag Register 2 and Register 0xFEC6—Latched Flag Register 2 (1 = Fault, 0 = Normal Operation) Bits Bit Name R/W Description Register Action 7 POWER_SUPPLY_B R Channel B power supply is off and the PWM outputs are disabled. This bit stays high until PSON_B is asserted. None 6 PGOOD_B R Power-good fault on Channel B. This flag is set when the UVP_B, POWER_SUPPLY_B, EEPROM_CRC, or SOFTSTART_FILTER_B flag is set. The ACSNS and OTW2 flags can also be programmed to be included. 0xFE09, 0xFE78, 0xFE8A PGOOD_B pin set low 5 CS1_B_OCP R The voltage at CS1_B is above the 1.2 V threshold. 0xFE00, 0xFE71 Programmable 4 CS2_B_OCP R The voltage at CS2_B is above its threshold. 0xFE01, 0xFE19 Programmable 3 UVP_B R VS_B is below its threshold. 0xFE03, 0xFE29 Programmable 2 OVP_B R OVP_B is above its threshold. 0xFE02, 0xFE27 Programmable 1 LIGHTLOAD_B R Channel B is in light load mode (CS2_B current is below the light load threshold). 0xFE1B, 0xFE6A Programmable 0 VS_SET_ERR_B R The intended VS_B reference setting is outside the allowed range. 0xFE1F, 0xFE21 None Table 132. Register 0xFEC2—Flag Register 3 and Register 0xFEC7—Latched Flag Register 3 (1 = Fault, 0 = Normal Operation) Bits Bit Name R/W Description Register Action 7 Reserved R Reserved. 6 VDD_OV R Overvoltage condition (VDD is above limit). The I2C interface remains functional, but a PSON toggle is required to restart the power supply. 0xFE06 Programmable 5 CS_OCP R The voltage at CS is above the 1.2 V threshold. 0xFE04, 0xFE6F Programmable 4 OTP2 R Temperature of Zone 2 is above the OTP2 threshold. 0xFE05, 0xFE76 Programmable 3 OTP1 R Temperature of Zone 1 is above the OTP1 threshold. 0xFE05, 0xFE75 Programmable 2 ACSNS R ACSNS is below its threshold. 0xFE04, 0xFE78 Programmable 1 EEPROM_CRC R The downloaded EEPROM contents are incorrect. Immediate shutdown 0 FLAGIN R The external flag pin (FLGI/SYNI) is set. 0xFE06, 0xFE0F Programmable Table 133. Register 0xFEC3—Flag Register 4 and Register 0xFEC8—Latched Flag Register 4 (1 = Fault, 0 = Normal Operation) Bits Bit Name R/W Description Register Action 7 Reserved R Reserved. 6 POWER_SUPPLY_C R Channel C power supply is off and the PWM outputs are disabled. This bit stays high until PSON_C is asserted. None 5 FLAGOUT R The FLGO/SYNO pin is set in response to the LIGHTLOAD_A or LIGHTLOAD_B flag. 0xFE0F None 4 EEPROM_UNLOCKED R The EEPROM is unlocked. None 3 SOFTSTART_FILTER_B R Channel B soft start filter is in use. 0xFE3F None 2 SOFTSTART_FILTER_A R Channel A soft start filter is in use. 0xFE3E None 1 MODULATION_B R Channel B digital filter is at its minimum or maximum limit. 0xFE3D None 0 MODULATION_A R Channel A digital filter is at its minimum or maximum limit. 0xFE3C None |
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