ADP1053ACPZ-R7 datasheet(83/84 Pages) AD

83 / 84 page

Data Sheet

ADP1053

Rev. A | Page 83 of 84

Table 143. Register 0xFED7—RTD1 Value

Bits

Bit Name

R/W

Description

[15:4]

RTD1 temperature

value

This register contains the 12-bit RTD1 temperature information as determined from the RTD1 pin.

The range of the RTD1 input pin is from 0 V to 1.6 V. Each LSB corresponds to 390.6 μV. At 0 V input,

the value in this register is 0. The nominal voltage at this pin is 1 V. At 1 V input, the value in these

bits is 0xA00 (2560 decimal).

[3:0]

Reserved

Reserved.

Table 144. Register 0xFED8—RTD2 Value

Bits

Bit Name

R/W

Description

[15:4]

RTD2 temperature

value

This register contains the 12-bit RTD2 temperature information as determined from the RTD2 pin.

The range of the RTD2 input pin is from 0 V to 1.6 V. Each LSB corresponds to 390.6 μV. At 0 V input,

the value in this register is 0. The nominal voltage at this pin is 1 V. At 1 V input, the value in these

bits is 0xA00 (2560 decimal).

[3:0]

Reserved

Reserved.

Table 145. Register 0xFED9—ACSNS Value

Bits

Bit Name

R/W

Description

[15:5]

ACSNS voltage value

This register contains the 11-bit ACSNS voltage information. The range of the ACSNS input pin is

from 0 V to 1.6 V. Each LSB corresponds to 781.25 μV. At 0 V input, the value in this register is 0.

The nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0x500 (1280 decimal).

[4:0]

Reserved

Reserved.

Table 146. Register 0xFEDA—Channel A Duty Cycle Value

Bits

Bit Name

R/W

Description

[15:4]

Channel A duty cycle

value

This register contains the 12-bit duty cycle information for Channel A. The duty cycle is calculated

using the rising and falling edge timings of OUT1, OUT2, OUT5, or OUT6. If more than one of

these PWM outputs is assigned to Channel A, the PWM output used in the duty cycle calculation

is selected in the following order: OUT1, OUT2, OUT5, OUT6. Each LSB corresponds to 0.0244%

of the duty cycle. At 100% duty cycle, the value in this register is 0xFFF (4095 decimal).

[3:0]

Reserved

Reserved.

Table 147. Register 0xFEDB—Channel B Duty Cycle Value

Bits

Bit Name

R/W

Description

[15:4]

Channel B duty cycle

value

This register contains the 12-bit duty cycle information for Channel B. The duty cycle is calculated

using the rising and falling edge timings of OUT1, OUT2, OUT5, or OUT6. If more than one of

these PWM outputs is assigned to Channel B, the PWM output used in the duty cycle calculation

is selected in the following order: OUT1, OUT2, OUT5, OUT6. Each LSB corresponds to 0.0244%

of the duty cycle. At 100% duty cycle, the value in this register is 0xFFF (4095 decimal).

[3:0]

Reserved

Reserved.

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