ADP1053ACPZ-R7 datasheet(52/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 52 of 84

Register 0xFE08 specifies whether volt-second balance control is blanked during the soft start of the channel that is configured for volt-

second balance (Channel A or Channel C). Bit 7 of Register 0xFE72 selects the channel for volt-second balance control. Register 0xFE08

also specifies whether to disable the SR outputs (OUT3, OUT4, OUT7, and OUT8) during the soft start of their assigned channel. When

synchronous rectification is not disabled on a channel during soft start, the PWM output disable settings in Register 0xFE60 determine

whether the output is disabled.

Table 34. Register 0xFE08—Volt-Second Balance Blanking and SR Disable During Soft Start

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

ACSNS reenable

blank

R/W

This bit specifies whether the ACSNS flag is blanked during the flag reenable time.

0 = do not blank the ACSNS flag during the flag reenable time.

1 = blank the ACSNS flag during the flag reenable time.

First flag ID update

R/W

This bit specifies whether the first flag ID is saved in the EEPROM.

0 = first flag ID is not saved in the EEPROM.

1 = first flag ID is saved in the EEPROM.

Flag shutdown

timing

R/W

This bit specifies when the PWM outputs are shut down after a flag is triggered.

0 = PWM outputs are shut down at the end of the PWM cycle.

1 = PWM outputs are shut down immediately.

Volt-second balance

blanking

R/W

This bit specifies whether volt-second balance control is blanked during the soft start of the

channel that is enabled for volt-second balance control (Channel A or Channel C, as specified

by Bit 7 of Register 0xFE72).

0 = do not blank volt-second balance control during Channel A or Channel C soft start.

1 = blank volt-second balance control during Channel A or Channel C soft start.

Channel C SR disable

R/W

This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the

soft start of Channel C, if these outputs are assigned to Channel C.

0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C.

1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel C.

Channel B SR disable

R/W

This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the

soft start of Channel B, if these outputs are assigned to Channel B.

0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B.

1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel B.

Channel A SR disable

R/W

This bit specifies whether the SR outputs (OUT3, OUT4, OUT7, and OUT8) are disabled during the

soft start of Channel A, if these outputs are assigned to Channel A.

0 = do not disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A.

1 = disable OUT3, OUT4, OUT7, and OUT8 during soft start of Channel A.

Table 35. Register 0xFE09—PGOOD Debounce

Bits

Bit Name

R/W

Description

These bits set the PGOOD_B on debounce time, that is, the time from when the PGOOD_B on

condition is met to when the PGOOD_B flag is set.

Bit 7

Bit 6

Typical PGOOD_B On Debounce Time

0 ms

200 ms

320 ms

[7:6]

PGOOD_B on

debounce

R/W

600 ms

R/W

These bits set the PGOOD_B off debounce time, that is, the time from when the PGOOD_B off

condition is met to when the PGOOD_B flag is cleared.

Bit 5

Bit 4

Typical PGOOD_B Off Debounce Time

0 ms

200 ms

320 ms

[5:4]

PGOOD_B off

debounce

600 ms

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