ADP1053ACPZ-R7 datasheet(66/84 Pages) AD

66 / 84 page

ADP1053

Data Sheet

Rev. A | Page 66 of 84

BALANCE CONTROL REGISTERS

Balance control is based on the modulation from volt-second balance control or dual-phase current balance control. For volt-second

balance control, when the CS signal in the half cycle after the rising edge of OUT1 is higher than the CS signal in the half cycle after the

rising edge of OUT2, the modulation value increases. For dual-phase current balance control, when the CS1_A or CS2_A value is larger

than the CS1_B or CS2_B value, the modulation value increases.

Table 92. Register 0xFE62—Balance Control on OUT1 and OUT2

Bits

Bit Name

R/W

Description

tR2 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT2, tR2.

tR2 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tR2 right.

1 = negative sign. Increase of balance control modulation moves tR2 left.

tF2 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT2, tF2.

tF2 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tF2 right.

1 = negative sign. Increase of balance control modulation moves tF2 left.

tR1 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT1, tR1.

tR1 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tR1 right.

1 = negative sign. Increase of balance control modulation moves tR1 left.

tF1 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT1, tF1.

tF1 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tF1 right.

1 = negative sign. Increase of balance control modulation moves tF1 left.

Table 93. Register 0xFE63—Balance Control on OUT3 and OUT4

Bits

Bit Name

R/W

Description

tR4 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT4, tR4.

tR4 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tR4 right.

1 = negative sign. Increase of balance control modulation moves tR4 left.

tF4 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT4, tF4.

tF4 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tF4 right.

1 = negative sign. Increase of balance control modulation moves tF4 left.

tR3 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT3, tR3.

tR3 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tR3 right.

1 = negative sign. Increase of balance control modulation moves tR3 left.

tF3 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT3, tF3.

tF3 balance direction

R/W

0 = positive sign. Increase of balance control modulation moves tF3 right.

1 = negative sign. Increase of balance control modulation moves tF3 left.

Table 94. Register 0xFE64—Balance Control on OUT5, OUT6, OUT7, and OUT8

Bits

Bit Name

R/W

Description

tR8 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT8, tR8.

An increase of balance control modulation moves tR8 left.

tF8 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT8, tF8.

An increase of balance control modulation moves tF8 left.

tR7 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT7, tR7.

An increase of balance control modulation moves tR7 right.

tF7 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT7, tF7.

An increase of balance control modulation moves tF7 right.

tR6 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT6, tR6.

An increase of balance control modulation moves tR6 left.

tF6 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT6, tF6.

An increase of balance control modulation moves tF6 left.

tR5 balance setting

R/W

Setting this bit enables modulation from balance control on the rising edge of OUT5, tR5.

An increase of balance control modulation moves tR5 right.

tF5 balance setting

R/W

Setting this bit enables modulation from balance control on the falling edge of OUT5, tF5.

An increase of balance control modulation moves tF5 right.

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