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ADP1053ACPZ-R7 датащи(PDF) 78 Page - Analog Devices

номер детали ADP1053ACPZ-R7
подробное описание детали  3-Channel Digital
PDF  84 Pages
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производитель  AD [Analog Devices]
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ADP1053ACPZ-R7 датащи(HTML) 78 Page - Analog Devices

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ADP1053
Data Sheet
Rev. A | Page 78 of 84
Table 126. Register 0xFE86 and Register 0xFE87—VS_A/VS_B Slew Rate for Output Voltage Adjustment
Bits
Bit Name
R/W
Description
[7:4]
Reserved
R/W
Reserved.
These bits specify the slew rate.
Bit 3
Bit 2
Bit 1
Slew Rate
0
0
0
1.5625 mV/ms (4 LSB/ms)
0
0
1
3.125 mV/ms
0
1
0
6.25 mV/ms
0
1
1
12.5 mV/ms
1
0
0
25 mV/ms
1
0
1
50 mV/ms
1
1
0
100 mV/ms
[3:1]
Slew rate setting
R/W
1
1
1
200 mV/ms
0
Slew rate adjust
enable
R/W
Setting this bit enables output voltage adjustment with the slew rate specified by Bits[3:1].
Table 127. Register 0xFE88—Power Supply Software Reset Control
Bits
Bit Name
R/W
Description
[7:4]
Reserved
R/W
Reserved.
These bits specify the delay after the power supply is turned off and before the part is restarted.
Bit 3
Bit 2
Restart Delay
0
0
0 ms
0
1
500 ms
1
0
1 sec
[3:2]
Restart delay
R/W
1
1
2 sec
1
Channel B SW reset
GO
R/W
Setting this bit resets the Channel B power supply with a preset delay between the turning off
of the power supply and the restarting of the part. This restart delay is set using Bits[3:2].
0
Channel A SW reset
GO
R/W
Setting this bit resets the Channel A power supply with a preset delay between the turning off
of the power supply and the restarting of the part. This restart delay is set using Bits[3:2].
Table 128. Register 0xFE89—CS, CS1, and CS2 ADC Update Rate
Bits
Bit Name
R/W
Description
[7:2]
Reserved
R/W
Reserved.
These bits specify the update rate for the current value ADCs. By default, the current value ADCs
are updated every 10 ms.
Bit 1
Bit 0
Update Rate
0
0
10.5 ms
0
1
52.4 ms
1
0
104.9 ms
[1:0]
CSx value update rate
R/W
1
1
209.7 ms



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