ADP1053ACPZ-R7 datasheet(56/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 56 of 84

CHANNEL A/CHANNEL B CURRENT SENSE AND LIMIT SETTING REGISTERS

Table 40. Register 0xFE10—CS1_A Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS1_A gain trim

R/W

This value calibrates the CS1_A current sense gain. For more information, see the CS, CS1_A, and

CS1_B Gain Trim section.

Table 41. Register 0xFE11—CS1_B Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS1_B gain trim

R/W

This value calibrates the CS1_B current sense gain. For more information, see the CS, CS1_A, and

CS1_B Gain Trim section.

Table 42. Register 0xFE12—CS2_A Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS2_A gain trim

R/W

This value calibrates the CS2_A current sense gain. For more information, see the CS2_A and

CS2_B Gain Trim section.

Table 43. Register 0xFE13—CS2_B Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS2_B gain trim

R/W

This value calibrates the CS2_B current sense gain. For more information, see the CS2_A and

CS2_B Gain Trim section.

Table 44. Register 0xFE14—CS2_A Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2_A digital offset

trim

R/W

This register contains the CS2_A digital offset trim level. This value is used to calibrate the CS2_A

value. For more information, see the CS2_A and CS2_B Offset Trim section.

Table 45. Register 0xFE15—CS2_B Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2_B digital offset

trim

R/W

This register contains the CS2_B digital offset trim level. This value is used to calibrate the CS2_B

value. For more information, see the CS2_A and CS2_B Offset Trim section.

Table 46. Register 0xFE16—CS2_A Analog Offset Trim

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Analog trim polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[5:0]

CS2_A analog offset

trim

R/W

This value calibrates the CS2_A value. For more information, see the CS2_A and CS2_B Offset

Trim section.

Table 47. Register 0xFE17—CS2_B Analog Offset Trim

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Analog trim polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[5:0]

CS2_B analog offset

trim

R/W

This value calibrates the CS2_B value. For more information, see the CS2_A and CS2_B Offset

Trim section.

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