ADP1053ACPZ-R7 datasheet(60/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 60 of 84

SOFT START, DIGITAL FILTER, AND MODULATION SETTING REGISTERS

Table 64. Register 0xFE2A—Channel A Soft Start Ramp Rate

Bits

Bit Name

R/W

Description

[7:2]

Reserved

R/W

Reserved.

These bits set the output reference ramp rate during soft start for Channel A. The ramp time is

based on VREF = 2/3 full-scale range (FSR).

Bit 1

Bit 0

Typical Soft Start Ramp Rate

1.75 ms

10.5 ms

21.0 ms

[1:0]

Channel A soft start

ramp time

R/W

40.2 ms

Table 65. Register 0xFE2B—Channel B Soft Start Ramp Rate

Bits

Bit Name

R/W

Description

[7:2]

Reserved

R/W

Reserved.

These bits set the output reference ramp rate during soft start for Channel B. The ramp time is

based on VREF = 2/3 full-scale range (FSR).

Bit 1

Bit 0

Typical Soft Start Ramp Rate

1.75 ms

10.5 ms

21.0 ms

[1:0]

Channel B soft start

ramp time

R/W

40.2 ms

POLE LOCATION RANGE

ZERO

POLE

100Hz

500Hz

1kHz

5kHz

10kHz

Figure 41. Digital Filter Programmability

Table 66. Register 0xFE2C—Channel A Normal Mode Low Frequency Gain

Bits

Bit Name

R/W

Description

[7:0]

Channel A normal

mode low frequency

gain

R/W

This register specifies the low frequency gain of the feedback filter for Channel A in normal

mode. The gain is programmable over a 20 dB range (see Figure 41). Each LSB corresponds to

a 0.3 dB increase.

Table 67. Register 0xFE2D—Channel B Normal Mode Low Frequency Gain

Bits

Bit Name

R/W

Description

[7:0]

Channel B normal

mode low frequency

gain

R/W

This register specifies the low frequency gain of the feedback filter for Channel B in normal

mode. The gain is programmable over a 20 dB range (see Figure 41). Each LSB corresponds to

a 0.3 dB increase.

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