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ADP1053ACPZ-R7 датащи(PDF) 28 Page - Analog Devices |
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ADP1053ACPZ-R7 датащи(HTML) 28 Page - Analog Devices |
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28 / 84 page ![]() ADP1053 Data Sheet Rev. A | Page 28 of 84 The response to the UVP_A and UVP_B flags can be pro- grammed using Register 0xFE03. For more information, see the Protection Actions section and the Flag Configuration Registers section. During the soft start, PSON delay, and flag reenable time, the UVP_A and UVP_B flags are blanked. ACSNS FLAG The ACSNS flag (Bit 2 in Register 0xFEC2) is set when the voltage reading at ACSNS goes below the threshold that is programmed using Bits[5:2] of Register 0xFE78. The value in Bits[5:2] is compared with the four MSBs of the ACSNS value. For example, with an 11 kΩ/1 kΩ divider, Bits[5:2] of Register 0xFE78 are set to 0101 (5 decimal). These bits are compared with the four MSBs of the 8-bit ACSNS value. The ACSNS threshold is (1.6 V/16) × 5 × 12 = 6.00 V The debounce time of the flag can be set to 0 ms, 2.6 ms, 10.4 ms, or 100 ms using Bits[1:0] of Register 0xFE78. Because the ACSNS reading is the average value over every 1 ms, there is an additional debounce and delay time of up to 1 ms. The response to the ACSNS flag can be programmed using Register 0xFE04. For more information, see the Protection Actions section and the Flag Configuration Registers section. In addition, the user can optionally include the ACSNS flag in the PGOOD_A/PGOOD_B flags using Bit 7 of Register 0xFE78. The debounce time for the ACSNS flag when it is included in the PGOOD_A/PGOOD_B flags is different from that of the ACSNS flag itself. The debounce time can be set to 0 ms or 2.6 ms using Bit 6 of Register 0xFE78. OVERCURRENT PROTECTION (OCP) FLAGS The ADP1053 has a fast OCP function for CS, CS1_A, and CS1_B and an accurate OCP function for CS2_A and CS2_B. CS, CS1_A, CS1_B, CS2_A, and CS2_B have separate OCP circuits to provide protection for all three channels. The response to the OCP flags can be programmed using Register 0xFE00, Register 0xFE01, and Register 0xFE04. CS, CS1_A, and CS1_B Fast OCP Flags CS1_A OCP, CS1_B OCP, and CS OCP provide fast overcurrent protection for Channel A, Channel B, and Channel C, respectively. OCP protection is implemented with internal analog comparators, as shown in Figure 13 and Figure 14. When the voltage at the CS, CS1_A, or CS1_B pin exceeds the fixed 1.2 V threshold, the corre- sponding OCP flag is set (Bit 5 in Register 0xFEC0 for Channel A, Register 0xFEC1 for Channel B, and Register 0xFEC2 for Channel C). There is a 110 ns (max) propagation delay in the comparators. A blanking time of 0 ns, 40 ns, 80 ns, 120 ns, 200 ns, 400 ns, 600 ns, or 800 ns can be set to ignore the current spike at the beginning of the current signal. The blanking time is set using Register 0xFE6F, Register 0xFE70, and Register 0xFE71. During the blanking time, the OCP comparator output is ignored. The blanking time of the CS comparator is referenced to the rising edges of OUT1 and OUT2. The blanking time of the CS1_A and CS1_B comparators is referenced to the rising edge of OUT1, OUT2, OUT5, or OUT6 (programmable with Register 0xFE6B and Register 0xFE6C). A debounce time of 0 ns, 40 ns, 80 ns, or 120 ns (programmable with Register 0xFE6F, Register 0xFE70, and Register 0xFE71) can also be added to improve the noise immunity of the OCP circuit. The debounce time is the minimum time that the CS, CS1_A, or CS1_B signal must be continuously above the OCP threshold before the flag triggers an action. Figure 25 shows an example of CS OCP timing with the rising edge of OUT1 as the blanking time reference. After the CS_OCP flag is set, it is not cleared until the beginning of the next switching cycle. The latched CS_OCP flag is not cleared at the beginning of the switching cycle. The CS1_A_OCP and CS1_B_OCP flags function in the same way for Channel A and Channel B, respectively. t0 tS OUT1 CS OCP FLAG LATCHED OCP FLAG COMPARATOR OUTPUT tDEBOUNCE tBLANK tBLANK tDEBOUNCE CS THRESHOLD Figure 25. Fast OCP Flag Timing A flag timeout value can also be programmed using Bits[3:2] of Register 0xFE6F, Register 0xFE70, and Register 0xFE71. This timeout specifies the number of consecutive switching cycles with OCP triggered that must occur before the OCP flag can be set. In Figure 26, the flag timeout value is set to eight cycles. t0 CS OCP FLAG LATCHED OCP FLAG COMPARATOR OUTPUT CS THRESHOLD tS 2 tS 3 tS 4 tS 5 tS 6 tS 7 tS 8 tS 9 tS 10 tS Figure 26. Fast OCP Timeout |
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