ADP1053ACPZ-R7 datasheet(21/84 Pages) AD

21 / 84 page

Data Sheet

ADP1053

Rev. A | Page 21 of 84

LIGHT LOAD MODE AND PHASE SHEDDING

The ADP1053 can be configured to disable PWM outputs under

light load conditions based on the value of CS2_A and CS2_B.

This function is programmed in Register 0xFE69 (for Channel A)

and Register 0xFE6A (for Channel B) and can be used to imple-

ment phase shedding for multiphase operation. The light load

condition flags, LIGHTLOAD_A (Bit 1 of Register 0xFEC0) and

LIGHTLOAD_B (Bit 1 of Register 0xFEC1), are based on the

reading of CS2_A and CS2_B, respectively.

The light load current thresholds can be programmed indepen-

dently with Bits[3:0] of Register 0xFE1A and Register 0xFE1B.

Each LSB of the threshold setting represents 64 LSBs of the

12-bit CS2_A/CS2_B readings. Because the input range of the

CS2_A/CS2_B ADCs is 120 mV, each LSB of the threshold is

equal to 1.875 mV. When Bits[3:0] are set to 0, the light load

flag remains cleared.

Hysteresis is added to avoid switching between normal mode

and light load mode. The threshold setting is the value that

causes the part to enter light load mode. The value to exit light

load mode is 2.8125 mV (96 LSBs) greater than the threshold to

enter light load mode.

For example, in a system with a 2 mΩ sensing resistor, Bits[3:0]

of Register 0xFE1A are set to 1001 (9 decimal). Therefore, the

threshold to enter light load mode is

ILIGHTLOAD_IN = 9 × 1.875 mV/2 mΩ = 8.44 A

where ILIGHTLOAD_IN is the output current below which the part

enters light load mode.

The threshold to exit light load mode and enter forced PWM

mode is

ILIGHTLOAD_OUT = (9 × 1.875 mV + 2.8125 mV)/2 mΩ = 9.84 A

where ILIGHTLOAD_OUT is the output current above which the part

exits light load mode.

When a channel enters light load mode, the following actions

take place:

•

The LIGHTLOAD_A/LIGHTLOAD_B flag is set.

•

The configured PWM outputs (programmable using

•

The feedback digital filter changes to the values for the

light load condition.

When a channel exits light load mode, the light load flag is

cleared, the disabled PWM outputs are reenabled, and the

feedback filter changes back to the values for normal mode.

The signal at the FLGO/SYNO pin can be configured as a flag

output by setting Bit 3 of Register 0xFE0F. This signal can be

programmed to respond to either the LIGHTLOAD_A or

LIGHTLOAD_B flag using Bit 4 of Register 0xFE0F. The

polarity of the FLGO/SYNO pin can be set to inverted or

noninverted using Bit 5 of Register 0xFE0F.

ADP1053

VOUT

FLGO/SYNO

DRIVER

PWM OUTPUTS

Figure 20. Phase Shedding in Dual-Phase Buck Controller

POWER-GOOD SIGNALS

Each regulated channel of the ADP1053 has a power-good pin:

PGOOD_A for Channel A and PGOOD_B for Channel B. The

PGOOD_A or PGOOD_B fault flag (Bit 6 of Register 0xFEC0

or Register 0xFEC1) is set when the EEPROM_CRC, POWER_

SUPPLY_x, UVP_x, or SOFTSTART_FILTER_x flag is set. The

ACSNS and OTWx flags can also be included in the setting of

the PGOOD_A and PGOOD_B flags.

An overvoltage or overcurrent event does not directly trigger

PGOOD_x, but it can trigger a POWER_SUPPLY_x fault that

in turn triggers PGOOD_x. For example, if an overcurrent

condition sets the OCP flag and the configured response to

the OCP flag is to disable the appropriate PWM outputs, thus

causing the power supply output to fall, a POWER_SUPPLY_x

fault can be triggered that in turn triggers PGOOD_x. In the

same way, an overvoltage condition can also indirectly trigger

PGOOD_x.

The PGOOD_A and PGOOD_B pins are open-drain, active low

pins. The on and off debounce times for the PGOOD_A and

PGOOD_B fault flags are programmable for each flag at 0 ms,

200 ms, 320 ms, or 600 ms using Register 0xFE09.

SOFT START AND SHUTDOWN

PSON Control

The turning on and off of regulated Channel A is controlled by

the hardware PSON_A pin and/or the software PSON_A register,

depending on the configured settings in Register 0xFE79. In the

same way, the turning on and off of regulated Channel B is con-

trolled by the hardware PSON_B pin and/or the software PSON_B

The PSON_A and PSON_B pins and registers can be controlled

independently by different enable signals. The pins can also be

tied together and triggered by the same signal.

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