ADP1053ACPZ-R7 datasheet(74/84 Pages) AD

74 / 84 page

ADP1053

Data Sheet

Rev. A | Page 74 of 84

Table 113. Register 0xFE78—ACSNS Setting

Bits

Bit Name

R/W

Description

ACSNS flag included

in PGOOD

R/W

Setting this bit includes the ACSNS flag in the PGOOD_A and PGOOD_B flags. The debounce

time for this function is set with Bit 6.

Debounce of ACSNS

flag included in

PGOOD

R/W

This bit sets the debounce time of the ACSNS flag when it is included in the PGOOD_A and

PGOOD_B flags.

0 = 0 ms.

1 = 2.6 ms.

[5:2]

ACSNS threshold

R/W

These bits set the ACSNS threshold. This 4-bit value is compared with the four MSBs of the

ACSNS value register (Register 0xFED9). The hysteresis is 75 mV. When these bits are set to 0,

the ACSNS flag is always cleared. For more information, see the ACSNS Flag section.

These bits set the ACSNS flag debounce time.

Bit 1

Bit 0

Typical Debounce Time

0 ms

2.6 ms

10.4 ms

[1:0]

ACSNS flag

debounce time

R/W

100 ms

PSON REGISTERS

Table 114. Register 0xFE79—Channel A PSON Setting

Bits

Bit Name

R/W

Description

PSON_A polarity

R/W

Setting this bit inverts the polarity of the PSON_A pin signal when hardware PSON_A is used.

0 = normal mode. A high signal on the PSON_A pin turns on Channel A.

1 = inverted. A low signal on the PSON_A pin turns on Channel A.

Software PSON_A

R/W

When software PSON_A is used, setting this bit turns on Channel A.

These bits specify which signal or signals are used as the PSON_A control.

Bit 5

Bit 4

PSON_A Control Selection

Always on. Channel A is always on.

Hardware PSON_A. The PSON_A pin turns Channel A on and off.

Software PSON_A. Bit 6 turns Channel A on and off.

[5:4]

PSON_A control

hardware/software

selection

R/W

Software and hardware PSON_A. Both the PSON_A pin and Bit 6 must be set

to turn on Channel A.

These bits specify the delay from when the PSON_A signal is set to when the soft start of

Channel A begins.

Bit 3

Bit 2

Typical Delay Time

0 ms

50 ms

250 ms

[3:2]

PSON_A delay

R/W

1 sec

These bits specify the delay from when the PSON_A signal is cleared to when Channel A is

turned off.

Bit 1

Bit 0

Typical Delay Time

0 ms

50 ms

250 ms

[1:0]

PSOFF_A delay

R/W

1 sec

ADP1053ACPZ-R7 датащи(PDF) 74 Page - Analog Devices

ADP1053ACPZ-R7 датащи(HTML) 74 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL