ADP1053ACPZ-R7 datasheet(14/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 14 of 84

THEORY OF OPERATION

PWM OUTPUTS (OUT1 TO OUT8)

The eight PWM outputs of the ADP1053 can be configured

as two regulated channels with feedback control (Channel A

and Channel B) and one additional unregulated channel with

a fixed duty cycle (Channel C). The frequency of these channels

can be individually programmed from 50 kHz to 625 kHz using

respectively.

The PWM engine in the ADP1053 is highly flexible. For example,

the user can assign two PWM outputs to Channel A, two PWM

outputs to Channel B, and four PWM outputs to Channel C.

The user can also assign seven PWM outputs to Channel A

and the remaining PWM output to Channel B. Alternatively,

all eight PWM outputs can be assigned to Channel A for a

single-channel solution.

As an example, Figure 5 shows a typical application circuit

consisting of a buck preregulator followed by a fixed PWM full-

bridge topology with synchronous rectification. In this example,

only Channel A and Channel B are configured. As shown in

Figure 5, the OUT1, OUT2, OUT5, and OUT7 PWM outputs

are assigned to Channel A, and the OUT3, OUT4, OUT6, and

OUT8 PWM outputs are assigned to Channel B. The Analog

Devices, Inc., ADuM3210 iCoupler® device is used for isolation

between the primary and secondary power stages.

All three channels can be enabled to support soft start. Channel A

and Channel B use a closed-loop soft start scheme, which increases

the reference voltage linearly and uses the feedback to increase

the duty cycle gradually. When PWM outputs are assigned to

Channel C with a fixed duty cycle, the duty cycle increases line-

arly until it reaches the preset value. For more information, see

the Soft Start and Shutdown section.

Four of the eight PWM outputs (OUT3, OUT4, OUT7, and

OUT8) can also be enabled for use as synchronous rectifier (SR)

PWM control signals. These SR signals can be disabled during

the power supply soft start ramp time. In addition, the SR PWM

outputs can be programmed to initiate soft start when the outputs

are enabled. For more information, see the Synchronous Rectifier

(SR) Soft Start section.

All eight PWM outputs can be enabled or disabled using

Timing of PWM Rising and Falling Edges

The timing of the rising and falling edges of the PWM outputs

can be individually programmed. Special care must be taken to

avoid shootthrough and cross-conduction. It is recommended

that the ADP1053 graphical user interface (GUI) be used to

program these outputs.

tRX

tRY

tFY

tFX

t0, START OF

SWITCHING CYCLE

tS, END OF

SWITCHING CYCLE

OUTX

OUTY

tS/2

Figure 7. PWM Output Timing Diagram

timing, falling edge timing, channel assignment, modulation

schemes, and balance controls for the PWM outputs. For more

information, see the PWM Output Timing Registers section.

One bit sets the 180o phase shift for each PWM output. When

this bit is not set, the rising edge timing and the falling edge

timing are referenced to the start of the switching cycle of the

assigned channel (see tRX and tFX in Figure 7). When this bit is

set, the rising edge timing and the falling edge timing are

referred to half the switching cycle (see tRY and tFY in Figure 7).

Each LSB in the timing registers corresponds to a 5 ns step.

The edge timing cannot exceed one switching cycle. Therefore,

when the 180° phase shift is disabled, the edges are always

located between t0 and tS; when the 180° phase shift is enabled,

the edges are located between tS/2 and 3tS/2.

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