MPF0900AMBA2ES datasheet(131/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

VMONx_EN

VMONx monitoring

Disabled

Enabled

Table 173. VMONx enable bit

When the VMONx is enabled manually or in the Power-up sequence, a programmable blanking time is provided

to allow enough time for the external supply to ramp up and settle before allowing OV and UV monitoring to

detect faults. The default blanking timer is set on OTP via the OTP_VMONx_TSET[1:0] bits.

OTP_VMONx_TSET[1:0]

VMONx settling time

250 µs

500 µs

1000 µs

2500 µs

Table 174. VMONx settling time configuration bits

13.3.3.2 LDO2 / LDO3 external VMON operation

When the LDO2 or LDO3 is configured as an external voltage monitor (OTP_LDOx_MODE[1:0] = 11) the LDOx

output will not be enabled, and the LDOxOUT pin becomes an input to monitor an external voltage supply. In

this configuration, a weak internal pulldown resistor is enabled in order to detect a random pin disconnection at

the LDOxOUT pin.

The VLDOxMON OV/UV debounce time is set by the global OV_DNBC[1:0] and UV_DBNC[1:0] bits and all

other voltage monitoring functions are controlled by the corresponding LDOx bits as follows:

Bits

VLDOxMON operation

OTP_LDOx_UVTH[2:0]

Set the undervoltage monitoring threshold

OTP_LDOx_OVTH[2:0]

Set the overvoltage monitoring threshold

VLDOx_RUN[4:0]

Set the nominal voltage monitoring level during the RUN state

VLDOx_STBY[4:0]

Set the nominal voltage monitoring level during the Monitoring STANDBY state

Table 175. LDOx control bits in VMON mode

VLDOx_RUN[4:0] VLDOx_STBY[4:0]

VLDOxMON monitoring voltage

00000

External divider VREF = 0.50 V

00001

0.70 V

00010

0.75 V

00011

0.80 V

00100

0.85 V

00101

0.90 V

00110

0.95 V

00111

1.00 V

01000

1.05 V

Table 176. VLDOxMON monitoring voltage configuration bits

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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