MPF0900AMBA2ES datasheet(127/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_VAON_OVTH[1:0]

VAON OV threshold

103 %

105 %

107 %

109 %

Table 166. VAON OV threshold configuration bits

13.3.2.1 VAON as always-on regulator

When the VAON regulator is configured as an always-on regulator, the VAONMON block will be used during the

DBGOFF state to ensure the VAON is within regulation before the PF09 can start the Power-up sequence.

OV/UV conditions will be detected and debounced based on the configuration bits provided above, and the fault

reaction will be performed as described in section 16.6.3 VAON Fault Management.

13.3.2.2 VAON as system regulator

When VAON is operating as a system regulator, the VAONMON is enabled during the Power-up sequence to

ensure the system has proper power before placing the MCU out of reset, and it will continue monitoring for OV/

UV fault conditions based on the VAONMON configuration shown above.

Fault reaction will be performed as described in section 16.6.2 System Regulators and External VMON Fault

Management.

13.3.3 External voltage monitoring

The PF09 features two dedicated external voltage monitors (VMON1 and VMON2) with selectable voltage

references, to allow seamless monitoring of an external supply with dynamic voltage scaling (DVS) capability.

Two additional external voltage monitors are available at the LDO2 and LDO3 outputs, if the LDO regulators are

not needed in the system.

13.3.3.1 VMON1 / VMON2

VMON1 and VMON2 are dedicated voltage monitors provided to allow the PF09 to monitor up to two external

voltages generated outside the device. In such scenarios, the PF09 becomes the main power management

safety controller to detect and notify when an OV/UV condition is present in the external voltage supplies.

Each VMON pin is provided with a weak internal pulldown resistor in order to detect a random pin disconnection

at the VMONx pin.

The undervoltage monitoring threshold for the VMONx block is set in the OTP registers via the

OTP_VMONx_UVTH[2:0] bits.

OTP_VMONx_UVTH[2:0]

UV threshold

000

96.5 %

001

96.0 %

010

95.5 %

011

95.0 %

100

94.5 %

Table 167. VMONx UV threshold configuration bits

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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