MPF0900AMBA2ES datasheet(135/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

All parameters are specified at TA = -40 °C to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5 V,

VSWxFB = 3.3 V (SW1), 1.0 V (SW2/SW3), 0.8 V(SW4/SW5), 3.3 V (LDO Regulator), 1.8 V (VAON), and TA = 25 °C unless

otherwise noted. MONx applies to all internal voltage monitors: VSWxMON, VLDOxMON, VMONx and VAONMON.

Symbol

Description

Min

Typ

Max

Unit

tUVDBN2_

VAONMON

VAONMON UV debounce

• UV_DBNC[1:0] = 10

µs

tUVDBN3_

VAONMON

VAONMON UV debounce

• UV_DBNC[1:0] = 11

µs

VOVACC_

VAONMON

VAONMON OV threshold accuracy

-2

–

VOVHYS_

VAONMON

VAONMON OV hysteresis

• Voltage difference between OV rising and falling thresholds

–

tOVDBN0_

VAONMON

VAONMON OV debounce

• OV_DBNC[1:0] = 00

µs

tOVDBN1_

VAONMON

VAONMON OV debounce

• OV_DBNC[1:0] = 01

µs

tOVDBN2_

VAONMON

VAONMON OV debounce

• OV_DBNC[1:0] = 10

105

µs

tOVDBN3_

VAONMON

VAONMON OV debounce

• OV_DBNC[1:0] = 11

125

160

µs

Table 180. Voltage monitor electrical characteristics...continued

13.4 Clock management

The PF09 features an advanced clock management scheme, providing top-level control of the internal clock

tree generation as well as external clock synchronization. It incorporates various analog blocks managed by a

digital clock management interface supporting all the interaction among them.

• Low-power 100 kHz oscillator

• Internal high-frequency oscillator with programmable frequency

• Clock watchdog monitor

• Phase-locked loop (PLL)

13.4.1 High-frequency clock

The PF09 features an internal high-frequency clock with programmable frequency between 16 MHz and 20

MHz. The high-frequency clock provides clocking signals to support various digital functions, and to support the

generation of the switching frequency for the five buck converters, when the device is set to operate solely with

the internal clock.

The PF09 relies on the high-frequency clock to perform most of the system monitoring during the RUN and

Monitored STANDBY states, and it is disabled during the Low-power STANDBY state and other Low-power OFF

states to achieve minimum power consumption in these states.

13.4.1.1 Manual frequency tuning

The high-frequency clock is programmable via the CLK_FREQ [3:0] bits, to allow manual frequency tuning from

16 MHz to 24 MHz. When the device is generating the clock for the buck regulators internally, the switching

frequency will be proportional to the selected frequency in the internal clock (divided by 8), allowing a selectable

switching frequency range from 2 MHz to 3 MHz.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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