AD9557SLASHPCBZ datasheet(26/92 Pages) AD

26 / 92 page

AD9557

Data Sheet

Rev. A | Page 26 of 92

Program the System Clock and Free Run Tuning Word

The system clock multiplier (SYSCLK) parameters are at

is at Register 0x0300 to Register 0x0303. Use the following steps

for optimal performance:

Set the system clock PLL input type and divider values.

Set the system clock period.

It is essential to program the system clock period because

many of the AD9557 subsystems rely on this value.

Set the system clock stability timer.

It is highly recommended that the system clock stability

timer be programmed. This is especially important when

using the system clock multiplier and also applies when

using an external system clock source, especially if the

external source is not expected to be completely stable

when power is applied to the AD9557. The system clock

stability timer specifies the amount of time that the system

clock PLL must be locked before the part declares that the

system clock is stable. The default value is 50 ms.

Program the free run tuning word.

The free run frequency of the digital PLL (DPLL) determines

the frequency appearing at the APLL input when free run

mode is selected. The free run tuning word is at Register

0x0300 to Register 0x0303. The correct free run frequency

is required for the APLL to calibrate and lock correctly.

Set user free run mode (Register 0x0A01[5] = 1b).

Initialize and Calibrate the Output PLL (APLL)

The registers controlling the APLL are at Register 0x0400 to

DPLL output (which is usually 175 MHz to 200 MHz) to a

frequency in the 3.35 GHz to 4.05 GHz range. After the system

clock is configured and the free run tuning word is set in

APLL VCO calibration bit (Register 0x0405[0]) and issue an I/O

update (Register 0x0005[0]). This process performs the APLL

VCO calibration. VCO calibration ensures that, at the time of

calibration, the dc control voltage of the APLL VCO is centered

in the middle of its operating range. It is important to remember

the following points when calibrating the APLL VCO:

•

The system clock must be stable.

•

The APLL VCO must have the correct frequency from

the 30-bit DCO (digitally controlled oscillator) during

calibration.

•

The APLL VCO must be recalibrated any time the APLL

frequency changes.

•

APLL VCO calibration occurs on the low-to-high transition

of the manual APLL VCO calibration bit, and this bit is not

autoclearing. Therefore, this bit must be cleared (and an

I/O update issued) before another APLL calibration is started.

•

The best way to monitor successful APLL calibration is to

monitor Bit 2 in Register 0x0D01 (APLL lock).

Program the Clock Distribution Outputs

The APLL output goes to the clock distribution block. The

clock distribution parameters reside in Register 0x0500 to

•

Output power-down control

•

Output enable (disabled by default)

•

Output synchronization

•

Output mode control

•

Output divider functionality

See the Clock Distribution section for more information.

Generate the Output Clock

If Register 0x0500[1:0] is programmed for automatic clock

distribution synchronization via the DPLL phase or frequency

lock, the synthesized output signal appears at the clock distribution

outputs. Otherwise, set and then clear the soft sync clock

distribution bit (Register 0x0A02, Bit 1) or use a multifunction

pin input (if programmed for use) to generate a clock distribution

sync pulse, which causes the synthesized output signal to appear

at the clock distribution outputs.

Program the Multifunction Pins (Optional)

This step is required only if the user intends to use any of the

multifunction pins for status or control. The multifunction pin

parameters are at Register 0x0200 to Register 0x0208.

Program the IRQ Functionality (Optional)

This step is required only if the user intends to use the IRQ feature.

The IRQ monitor registers are at Register 0x0D02 to Register

0x0D09. If the desired bits in the IRQ mask registers at Register

0x020A to Register 0x020F are set high, the appropriate IRQ

monitor bit at Register 0x0D02 to Register 0x0D07 is set high

when the indicated event occurs.

Individual IRQ events are cleared by using the IRQ clearing

registers at Register 0x0A04 to Register 0x0A09 or by setting

the clear all IRQs bit (Register 0x0A03[1]) to 1b.

The default values of the IRQ mask registers are such that

interrupts are not generated. The IRQ pin mode default is open-

drain NMOS.

Program the Watchdog Timer (Optional)

This step is required only if the user intends to use the watchdog

timer. The watchdog timer control is in Register 0x0210 and

The watchdog timer is useful for generating an IRQ after a fixed

amount of time. The timer is reset by setting the clear watchdog

timer bit (Register 0x0A03[0]) to 1b.

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