AD9557SLASHPCBZ datasheet(87/92 Pages) AD

87 / 92 page

Data Sheet

AD9557

Rev. A | Page 87 of 92

Table 112. EEPROM Storage Sequence for General Configuration Settings

Address

Bits

Bit Name

Description

0x0E17

[7:0]

General

The default value of this register is 0x11, which the controller interprets as a data

instruction. Its decimal value is 17, so this tells the controller to transfer 18 bytes of data

(17 + 1), beginning at the address specified by the next two bytes. The controller stores

0x11 in the EEPROM and increments the EEPROM address pointer.

0x0E18

[7:0]

0x0E19

[7:0]

The default value of these two registers is 0x0200. Note that Register 0x0E18 and

respectively. Because the previous register contains a data instruction, these two

registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in

the EEPROM and increments the EEPROM pointer by 2. It then transfers 18 bytes from

the register map (beginning at Address 0x0200) to the EEPROM and increments the

EEPROM address pointer by 19 (18 data bytes and one checksum byte). The 18 bytes

transferred correspond to the general configuration parameters in the register map.

Table 113. EEPROM Storage Sequence for DPLL Settings

Address

Bits

Bit Name

Description

0x0E1A

[7:0]

DPLL

The default value of this register is 0x2E, which the controller interprets as a data

instruction. Its decimal value is 46, so this tells the controller to transfer 47 bytes of data

(46 + 1), beginning at the address specified by the next two bytes. The controller stores

0x2E in the EEPROM and increments the EEPROM address pointer.

0x0E1B

[7:0]

0x0E1C

[7:0]

The default value of these two registers is 0x03. Note that Register 0x0E1B and

respectively. Because the previous register contains a data instruction, these two

registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in

the EEPROM and increments the EEPROM pointer by 2. It then transfers 47 bytes from

the register map (beginning at Address 0x0300) to the EEPROM and increments the

EEPROM address pointer by 48 (47 data bytes and one checksum byte). The 47 bytes

transferred correspond to the DPLL parameters in the register map.

Table 114. EEPROM Storage Sequence for APLL Settings

Address

Bits

Bit Name

Description

0x0E1D

[7:0]

APLL

The default value of this register is 0x08, which the controller interprets as a data instruction.

Its decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1),

beginning at the address specified by the next two bytes. The controller stores 0x08 in

the EEPROM and increments the EEPROM address pointer.

0x0E1E

[7:0]

0x0E1F

[7:0]

The default value of these two registers is 0x0400. Note that Register 0x0E1E and

respectively. Because the previous register contains a data instruction, these two registers

define a starting address (in this case, 0x0400). The controller stores 0x0400 in the EEPROM

and increments the EEPROM pointer by 2. It then transfers nine bytes from the register

map (beginning at Address 0x0400) to the EEPROM and increments the EEPROM address

pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred

correspond to APLL parameters in the register map.

Table 115. EEPROM Storage Sequence for Clock Distribution Settings

Address

Bits

Bit Name

Description

0x0E20

[7:0]

Clock distribution

The default value of this register is 0x15, which the controller interprets as a data instruction.

Its decimal value is 21, so this tells the controller to transfer 22 bytes of data (21+1),

beginning at the address specified by the next two bytes. The controller stores 0x15 in

the EEPROM and increments the EEPROM address pointer.

0x0E21

[7:0]

0x0E22

[7:0]

The default value of these two registers is 0x0500. Note that Register 0x0E21 and

respectively. Because the previous register contains a data instruction, these two registers

define a starting address (in this case, 0x0500). The controller stores 0x0500 in the EEPROM

and increments the EEPROM pointer by 2. It then transfers 22 bytes from the register map

(beginning at Address 0x0500) to the EEPROM and increments the EEPROM address

pointer by 23 (22 data bytes and one checksum byte). The 22 bytes transferred correspond to

the clock distribution parameters in the register map.

0x0E23

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update

instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address

pointer.

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