AD9557SLASHPCBZ datasheet(82/92 Pages) AD

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AD9557

Data Sheet

Rev. A | Page 82 of 92

QUICK IN/OUT FREQUENCY SOFT PIN CONFIGURATION (REGISTER 0x0C00 TO REGISTER 0x0C08)

Table 97. Soft Pin Program Setting

Address

Bits

Bit Name

Description

[7:1]

Reserved

0x0C00

Enable Soft Pin

Section 1

0 (default) = disables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 and

1 = enables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 and Register

0x0C02) when the PINCONTROL pin is low at startup and/or reset.

The register in Soft Pin Section 1 configures the part into one of 256 preconfigured input-to-

output frequency translations stored in the on-chip ROM.

The registers in Soft Pin Section 1 (Register 0x0C00 to Register 0x0C02) are ignored when the

PINCONTROL pin is high at power-up and/or reset (which means the hard pin program is enabled).

[7:4]

Output frequency

selection

Selects one of 16 predefined output frequencies as ouptut frequency of the desired frequency

translation and reprogram the free run TW, N2, RF div, and M0 to M3 divider with the value

stored in the ROM.

0x0C01

[3:0]

Input frequency

selection

Selects one of 16 predefined input frequencies as the input frequency of the desired frequency

translation and reprogram the reference period, R divider, N1, FRAC1, and MOD1 in four REF

profiles with the value stored in the ROM.

0x0C02

[7:2]

Reserved

Reserved.

[1:0]

System clock PLL

ref selection

Selects one of the four predefined system PLL references for the desired frequency translation

and reprogram the system PLL configuration with the value stored in the ROM. To load values

from ROM, user must write Register 0x0C07[0] = 1 after writing this value.

Equivalent System Clock PLL Settings,

System

PLL Ref

Bit 1

Bit 0

12 Bits

24.576 MHz XTAL, ×2 on, N = 16

49.152 MHz XTAL, ×2 on, N = 8

24.576 MHz XO, ×2 off, N = 32

49.152 MHz XO, ×2 off, N = 16

0x0C03

[7:1]

Reserved

Reserved.

Enable Soft Pin

Section 2

0 (default) = disables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to

1 = enables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to Register 0x0C06)

when PINCONTROL pin is low.

[7:4]

Reserved

Reserved.

[3:2]

REFB frequency scale

Scales selected input frequency (defined by Register 0x0C01[3:0]) for REFB.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

For example, if the selected input frequency is 622.08 MHz and Register 0x0C04[3:2] = 11b,

the new input frequency should be 622.08 MHz/16 = 38.8 MHz

0x0C04

[1:0]

REFA frequency scale

Scales selected input frequency (defined by Register 0x0C01[3:0]) for REFA.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

0x0C05

[7:4]

Reserved

Reserved.

[3:2]

Channel 1 output

frequency scale

Scales selected output frequency (defined by Register 0x0C01[7:4]) for Channel Divider 1 output.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

[1:0]

Channel 0 output

frequency scale

Scales selected output frequency (defined by Register 0x0C01[7:4]) for Channel Divider 0 output.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

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