AD9557SLASHPCBZ datasheet(32/92 Pages) AD

32 / 92 page

AD9557

Data Sheet

Rev. A | Page 32 of 92

During any given PFD cycle, the detector either adds water with

the fill bucket or removes water with the drain bucket (one or the

other but not both). The decision of whether to add or remove

water depends on the threshold level specified by the user. The

phase lock threshold value is a 16-bit number stored in the profile

registers and is expressed in picoseconds (ps). Thus, the phase lock

threshold extends from 0 ns to ±65.535 ns and represents the

magnitude of the phase error at the output of the PFD.

The phase lock detector compares each phase error sample at

the output of the PFD to the programmed phase threshold value.

If the absolute value of the phase error sample is less than or equal

to the programmed phase threshold value, then the detector

control logic dumps one fill bucket into the tub. Otherwise, it

removes one drain bucket from the tub. Note that it is not the

polarity of the phase error sample, but its magnitude relative to

the phase threshold value, that determines whether to fill or drain.

If more filling is taking place than draining, the water level in

the tub eventually rises above the high water mark (+1024),

which causes the phase lock detector to indicate lock. If more

draining is taking place than filling, then the water level in the tub

eventually falls below the low water mark (−1024), which causes

the phase lock detector to indicate unlock. The ability to specify

the threshold level, fill rate, and drain rate enables the user to

tailor the operation of the phase lock detector to the statistics of

the timing jitter associated with the input reference signal.

Note that whenever the AD9557 enters the free run or holdover

mode, the DPLL phase lock detector indicates an unlocked state.

However, when the AD9557 performs a reference switch, the

lock detector state prior to the switch is preserved during the

transition period.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that

of the phase lock detector. The only difference is that the fill or

drain decision is based on the period deviation between the

reference and feedback signals of the DPLL instead of the phase

error at the output of the PFD.

The frequency lock detector uses a 24-bit frequency threshold

threshold value extends from 0 μs to ±16.777215 μs. It represents

the magnitude of the difference in period between the reference

and feedback signals at the input to the DPLL. For example,

if the reference signal is 1.25 MHz and the feedback signal is

1.38 MHz, then the period difference is approximately 75.36 ns

(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).

Frequency Clamp

The AD9557 DPLL features a digital tuning word clamp that

ensures that the DPLL output frequency stays within a defined

range. This feature is very useful to eliminate undesirable behavior

in cases where the reference input clocks may be unpredictable.

The tuning word clamp is also useful to guarantee that the APLL

never loses lock, by ensuring that the APLL VCO frequency

stays within its tuning range.

Frequency Tuning Word History

The AD9557 has the ability to track the history of the tuning

word samples generated by the DPLL digital loop filter output.

It does so by periodically computing the average tuning word

value over a user-specified interval. This average tuning word is

used during holdover mode to maintain the average frequency

when no input references are present.

LOOP CONTROL STATE MACHINE

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another. The AD9557 handles a

reference switchover by briefly entering holdover mode, loading

the new DPLL parameters, and then immediately recovering.

During the switchover event, however, the AD9557 preserves

the status of the lock detectors to avoid phantom unlock

indications.

Holdover

The holdover state of the DPLL is typically used when none

of the input references are present, although the user can also

manually engage holdover mode. In holdover mode, the output

frequency remains constant. The accuracy of the AD9557 in

holdover mode is dependent on the device programming and

availability of tuning word history.

Recovery from Holdover

When in holdover mode and a valid reference becomes available,

the device exits holdover operation. The loop state machine

restores the DPLL to closed-loop operation, locks to the selected

reference, and sequences the recovery of all the loop parameters

based on the profile settings for the active reference.

Note that, if the user holdover bit is set, the device does not

automatically exit holdover when a valid reference is available.

However, automatic recovery can occur after clearing the user

holdover bit (Bit 6 in Register 0x0A01).

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