AD9557SLASHPCBZ datasheet(84/92 Pages) AD

84 / 92 page

AD9557

Data Sheet

Rev. A | Page 84 of 92

IRQ Monitor (Register 0x0D02 to Register 0x0D07

If not masked via the IRQ mask registers (Register 0x0209 and Register 0x020A), the appropriate IRQ monitor bit is set to Logic 1 when the

indicated event occurs. These bits are cleared only via the IRQ clearing registers (Register 0x0A04 to Register 0A0B), the reset all IRQs bit

(Register 0x0A03[1]), or a device reset.

Table 100. IRQ Monitor for SYSCLK

Address

Bits

Bit Name

Description

[7:6]

Reserved

Reserved.

SYSCLK unlocked

Indicates a SYSCLK PLL state transition from locked to unlocked

SYSCLK locked

Indicates a SYSCLK PLL state transition from unlocked to locked

APLL unlocked

Indicates an output PLL state transition from locked to unlocked

APLL locked

Indicates an output PLL state transition from unlocked to locked

APLL cal ended

Indicates that APLL calibration is complete

0x0D02

APLL cal started

Indicates that APLL in APLL calibration has begun

Table 101. IRQ Monitor for Distribution Sync, Watchdog Timer and EEPROM

Address

Bits

Bit Name

Description

[7:5]

Reserved

Pin program end

Indicates successful completion of a ROM load operation

Output distribution sync

Indicates a distribution sync event

Watchdog timer

Indicates expiration of the watchdog timer

EEPROM fault

Indicates a fault during an EEPROM load or save operation

0x0D03

EEPROM complete

Indicates successful completion of an EEPROM load or save operation

Table 102. IRQ Monitor for the Digital PLL

Address

Bits

Bit Name

Description

Switching

Indicates that the DPLL is switching to a new reference

Closed

Indicates that the DPLL has entered closed-loop operation

Freerun

Indicates that the DPLL has entered free run mode

Holdover

Indicates that the DPLL has entered holdover mode

Frequency unlocked

Indicates that the DPLL has lost frequency lock

Frequency locked

Indicates that the DPLL has acquired frequency lock

Phase unlocked

Indicates that the DPLL has lost phase lock

0x0D04

Phase locked

Indicates that the DPLL has acquired phase lock

Table 103. IRQ Monitor for History Update, Frequency Limit and Phase Slew Limit

Address

Bits

Bit Name

Description

[7:5]

Reserved

History updated

Indicates the occurrence of a tuning word history update

Frequency unclamped

Indicates a frequency limiter state transition from clamped to unclamped

Frequency clamped

Indicates a frequency limiter state transition from unclamped to clamped

Phase slew unlimited

Indicates a phase slew limiter state transition from slew limiting to not slew limiting

0x0D05

Phase slew limited

Indicates a phase slew limiter state transition from not slew limiting to slew limiting

Table 104. IRQ Monitor for Reference Inputs

Address

Bits

Bit Name

Description

Reserved

REFB validated

Indicates that REFB has been validated

REFB fault cleared

Indicates that REFB has been cleared of a previous fault

REFB fault

Indicates that REFB has been faulted

Reserved

REFA validated

Indicates that REFA has been validated

REFA fault cleared

Indicates that REFA has been cleared of a previous fault

0x0D06

REFA fault

Indicates that REFA has been faulted

0x0D07

[7:0]

Reserved

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