AD9557SLASHPCBZ datasheet(3/92 Pages) AD

3 / 92 page

Data Sheet

AD9557

Rev. A | Page 3 of 92

General Configuration (Register 0x0200 to

IRQ Mask (Register 0x020A to Register 0x020F)...................68

DPLL Configuration (Register 0x0300 to Register 0x032E) .69

Output PLL Configuration (Register 0x0400 to

Output Clock Distribution (Register 0x0500 to

Reference Inputs (Register 0x0600 to Register 0x0602) ........76

DPLL Profile Registers (Register 0x0700 to

Operational Controls (Register 0x0A00 to

Quick In/Out Frequency Soft Pin Configuration

(Register 0x0C00 to Register 0x0C08) .....................................82

Status Readback (Register 0x0D00 to Register 0x0D14) .......83

EEPROM Control (Register 0x0E00 to Register 0x0E3C) ....86

EEPROM Storage Sequence (Register 0x0E10 to

Outline Dimensions........................................................................92

Ordering Guide ...........................................................................92

REVISION HISTORY

3/12—Rev. 0 to Rev. A

Change to Output Frequency Range Parameter, Table 6 ............. 6

Changes to Test Conditions/Comments Column, Table 9 .......... 8

Changed Name of Pin 21 in Figure 2............................................ 17

Changes to Table 20 ........................................................................ 18

Changes to Chip Power Monitor and Startup, Device Register

Programming Using a Register Setup File, and Registers That

Differ from the Defaults for Optimal Performance Sections .... 25

Changes to Initialize and Calibrate the Output PLL (APLL)

Section .............................................................................................. 26

Changes to Program the Reference Profiles Section; Changed

Lock the Digital PLL Section Name to Generate the Reference

Acquisition; Changes to Generate the Reference Acquisition

Section .............................................................................................. 27

Changes to Figure 35; Changed 225 MHz to 200 MHz and

3.45 GHz to 3.35 GHz in Overview Section ................................ 28

Changed 180 MHz to 175 MHz in DPLL Overview Section .... 30

Changed DPLL Output Frequency to DCO Frequency

Throughout; Changes to Programmable Digital Loop Filter

Section .............................................................................................. 31

Changes to System Clock Inputs Section..................................... 33

Changed VCO2 Lower Frequency to 3.35 GHz in Figure 39;

Changes to Output PLL (APLL) Section...................................... 35

Changed 1024 to 1023 in Clock Dividers Section;

Changes to Divider Synchronization Section.............................. 36

Changes to the Multifunction Pins (M0 to M3) Section ........... 37

Added the Programming the EEPROM to Configure an M Pin to

Control Synchronization of the Clock Distribution Section..... 42

Changes to the Power Supply Partitions Section ........................ 53

Changed 89.5° to 88.5° in DPLL Phase Margin Section ............ 54

Changes to Register 0x000A, Table 35 ......................................... 56

Changes to Register 0x0304, Table 35 .......................................... 57

Change to Default Value in Register 0x0400 and Register 0x0403;

Changes to Register 0x0405, Table 35 .......................................... 58

Change to Bit 0, Register 0x070E, Table 35 ................................. 59

Change to Bit 6, Register 0x0D01, Table 35................................. 63

Added Address 0x0E3D to Address 0xE45, Table 35 ................. 64

Changes to Description, Register 0x0005, Table 38;

Added Table 40, Renumbered Sequentially; Changes to

Descriptions, Register 0x000C and Register 0x000D, Table 41... 65

Changes to Summary Text, Register 0x0200 to

Changes to Register 0x0304, Table 54; Change to Bits[7:6],

Table 55............................................................................................. 69

Changes to Table Title, Table 63; Changes to Description,

Changes to Register 0x0405, Table 64 .......................................... 73

Changes to Description Column, Register 0x0500, Table 67;

Changes to Description Column, Register 0x0501, Bits[6:4]

and Bit 0, Table 68 ........................................................................... 74

Change to Description Column, Register 0x0505, Bits[6:4],

Table 70............................................................................................. 75

Change to Register 0x0600, Bits[7:2], Table 72 ........................... 76

Changes to Register 0x0707; Change to Register 0x070A,

Bits[3:0], Table 76............................................................................ 77

Changes to Register 0x0A01, Table 87 ......................................... 79

Changes to Table 96 ........................................................................ 81

Changes to Register 0x0D01, Bit 6 and Bit 1, Table 99 .............. 83

Added Table 123.............................................................................. 89

Changes to Table 124 ...................................................................... 90

Changes to Table 125 ...................................................................... 91

10/11—Revision 0: Initial Version

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