AD9557SLASHPCBZ datasheet(31/92 Pages) AD

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Data Sheet

AD9557

Rev. A | Page 31 of 92

Programmable Digital Loop Filter

The AD9557 loop filter is a third-order digital IIR filter that is

analogous to the third-order analog loop shown in Figure 37.

Figure 37. Third Order Analog Loop Filter

The AD9557 loop filter block features a simplified architecture

in which the user enters the desired loop characteristics directly

into the profile registers. This architecture makes the calculation

of individual coefficients unnecessary in most cases, while still

offering complete flexibility.

The AD9557 has two preset digital loop filters: high (88.5°) phase

margin and normal (70°) phase margin. The loop filter coefficients

are stored in Register 0x0317 to Register 0x0322 for high phase

margin and Register 0x0323 to Register 0x032E for normal phase

margin. The high phase margin loop filter is intended for

applications in which the closed-loop transfer function must

not have greater than 0.1 dB of peaking.

Bit 0 of Register 0x070E selects which filter is used for Profile A,

and Bit 0 of 0x074E selects the filter for Profile B.

The loop bandwidth for Profile A is set in Register 0x070F to

The two preset conditions should cover all of the intended

applications for the AD9557. For special cases where these

conditions must be modified, the tools for calculating these

coefficients are available by contacting Analog Devices directly.

DPLL Digitally Controlled Oscillator Free Run Frequency

The AD9557 uses a Σ-Δ modulator (SDM) as a digitally controlled

oscillator (DCO). The DCO free run frequency can be calculated by

FTW

SYS

freerun

dco

where FTW0 is the value in Register 0x0300 to Register 0x0303,

and fSYS is the system clock frequency. See the System Clock

section for information on calculating the system clock frequency.

Adaptive Clocking

The AD9557 can support adaptive clocking applications such as

asynchronous mapping and demapping. In these applications,

the output frequency can be dynamically adjusted by up to

±100 ppm from the nominal output frequency without manually

breaking the DPLL loop and reprogramming the part. This

function is supported for REFA only, not REFB.

The following registers are used in this function:

•

Writing to these registers requires an I/O update by writing

0x01 to Register 0x0005 before the new values take effect.

To make small adjustments to the output frequency, the user

can vary the FRAC1 and issue an I/O update. The advantage to

using only FRAC1 to adjust the output frequency is that the

DPLL does not briefly enter holdover. Therefore, the FRAC1 bit

can be updated as fast as the phase detector frequency of the DPLL.

Writing to the N1 and MOD1 dividers allows for larger changes

to the output frequency. When the AD9557 detects that the N1

or MOD1 values have changed, it automatically enters and exits

holdover for a brief instant without any disturbance in the output

frequency. This limits how quickly the output frequency can be

adapted.

It is important to realize that the amount of frequency adjustment

is limited to ±100 ppm before the output PLL (APLL) needs

a recalibration. Variations that are larger than ±100 ppm are

possible, but the ability of the AD9557 to maintain lock over

temperature extremes may be compromised.

It is also important to remember that the rate of change in

output frequency depends on the DPLL loop bandwidth.

DPLL Phase Lock Detector

The DPLL contains an all-digital phase lock detector. The user

controls the threshold sensitivity and hysteresis of the phase

detector via the profile registers.

The phase lock detector behaves in a manner analogous to water in

a tub (see Figure 38). The total capacity of the tub is 4096 units

with −2048 denoting empty, 0 denoting the 50% point, and

+2048 denoting full. The tub also has a safeguard to prevent

overflow. Furthermore, the tub has a low water mark at −1024

and a high water mark at +1024. To change the water level, the

user adds water with a fill bucket or removes water with a drain

bucket. The user specifies the size of the fill and drain buckets

via the 8-bit fill rate and drain rate values in the profile registers.

2048

–2048

1024

–1024

LOCK LEVEL

UNLOCK LEVEL

LOCKED

UNLOCKED

STATE

FILL

RATE

DRAIN

RATE

Figure 38. Lock Detector Diagram

The water level in the tub is what the lock detector uses to deter-

mine the lock and unlock conditions. When the water level is

below the low water mark (−1024), the detector indicates an

unlock condition. Conversely, whenever the water level is above the

high water mark (+1024), the detector indicates a lock condition.

When the water level is between the marks, the detector holds

its last condition. This concept appears graphically in Figure 38,

with an overlay of an example of the instantaneous water level

(vertical) vs. time (horizontal) and the resulting lock/unlock states.

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