AD9557SLASHPCBZ datasheet(74/92 Pages) AD

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AD9557

Data Sheet

Rev. A | Page 74 of 92

OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)

Table 67. Distribution Output Synchronization Settings

Address

Bits

Bit Name

Description

[7:6]

Reserved

Reserved.

Mask Channel 1 sync

Masks the synchronous reset to the Channel 1 divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 1 from the static sync state,

thus allowing the Channel 1 divider to toggle. Channel 1 ignores all sync events while this

bit is set. Setting this bit does not enable the output drivers connected to this channel.

In addition, the output distribution sync also depends on the setting of Register 0x0405[3].

Mask Channel 0 sync

Masks the synchronous reset to the Channel 0 divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 0 from the static sync state,

thus allowing the Channel 0 divider to toggle. Channel 0 ignores all sync events while this

bit is set. Setting this bit does not enable the output drivers connected to this channel.

In addition, the output distribution sync also depends on the setting of Register 0x0405[3].

Reserved

Reserved.

Sync source selection

Selects the sync source for the clock distribution output channels.

0 (default) = direct. The sync pulse occurs on the next I/O update.

1 = active reference.

Note that the output distribution sync also depends on the APLL being calibrated and

locked, unless Register 0x0405[3] = 1b.

0x0500

[1:0]

Automatic sync mode

Autosync mode.

00 = disabled. A sync command must be issued manually or by using the sync mask bits

in this register (Bits[5:4]).

01 = sync on DPLL frequency lock.

10 (default) = sync on DPLL phase lock.

11 = reserved.

Table 68. Distribution OUT0 Setting

Address

Bits

Bit Name

Description

0x0501

Enable 3.3 V CMOS driver

0 (default) = disables 3.3 V CMOS driver, and OUT0 logic is controlled by Register 0x0501[6:4]

1 = enables 3.3 V CMOS driver as operating mode of OUT0.

This bit should be set to 1b only if Bits[6:4] are in CMOS mode.

[6:4]

OUT0 format

These bits set the OUT0 driver mode.

000 = PD, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2]

OUT0 polarity

Controls the OUT0 polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, nevative.

OUT0 drive strength

Controls the output drive capability of OUT0.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode).

Note that this is only in 3.3 V CMOS mode for CMOS strength. 1.8 V CMOS has only the

low drive strength.

Enable OUT0

Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled).

This bit does not enable/disable OUT0 if Bit 7 of this register is set to 1.

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