AD9557SLASHPCBZ datasheet(28/92 Pages) AD

28 / 92 page

AD9557

Data Sheet

Rev. A | Page 28 of 92

THEORY OF OPERATION

SPI/I2C

SERIAL PORT

EEPROM

REF MONITORING

AUTOMATIC

SWITCHING

÷N1

÷N2

÷N3

÷2

÷M0

OUT0

OUT1

10-BIT

INTEGER

DIVIDERS

MAX 1.25GHz

÷M1

×2

PFD/CP

RF DIVIDER 1

÷3 TO ÷11

XO OR XTAL

XO FREQUENCIES

10MHz TO 180MHz

XTAL: 10MHz TO 50MHz

RF DIVIDER 2

÷3 TO ÷11

fOUT = 360kHz TO 1.25GHz

INTEGER DIVIDER

OUTPUT PLL (APLL)

FRAC1/

MOD1

17-BIT

INTEGER

24b/24b

RESOLUTION

DIGITAL PLL (DPLL)

÷2

SPACE

R DIVIDER (20-BIT)

SYNC

RESET

PINCONTROL

M0 M1 M2 M3 IRQ

SPI/I2C

DIGITAL

LOOP

FILTER

TUNING

WORD

CLAMP AND

HISTORY

FREE RUN

LF_VCO2

PFD/CP

VCO2

3.35GHz

4.05GHz

ROM

AND

FSM

MULTIFUNCTION I/O PINS

(CONTROL AND STATUS

READBACK)

SYSTEM

CLOCK

PLL

÷2

AD9557

REFA

REFB

Figure 35. Detailed Block Diagram

OVERVIEW

The AD9557 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference, but with

jitter characteristics that are governed by the system clock, the

DCO, and the output PLL (APLL). The AD9557 supports up to

two reference inputs and input frequencies ranging from 2 kHz

to 1250 MHz. The core of this product is a digital phase-locked

loop (DPLL). The DPLL has a programmable digital loop filter

that greatly reduces jitter that is transferred from the active

reference to the output. The AD9557 supports both manual and

automatic holdover. While in holdover, the AD9557 continues

to provide an output as long as the system clock is present. The

holdover output frequency is a time average of the output

frequency history just prior to the transition to the holdover

condition. The device offers manual and automatic reference

switchover capability if the active reference is degraded or fails

completely. The AD9557 also has adaptive clocking capability

that allows the DPLL divider ratios to be changed while the

DPLL is locked.

The AD9557 has a system clock multiplier, a digital PLL (DPLL),

and an analog PLL (APLL). The input signal goes first to the DPLL,

which performs the jitter cleaning and most of the frequency

translation. The DPLL features a 30-bit digitally controlled

oscillator (DCO) output that generates a signal in the 175 MHz

to 200 MHz range. The DPLL output goes to an analog integer-N

PLL (APLL), which multiplies the signal up to the 3.35 GHz to

4.05 GHz range. That signal is then sent to the clock distribution

section, which has two divide-by-3 to divide-by-11 RF dividers

that are cascaded with 10-bit integer (divide-by-1 to divide-by-

1024) channel dividers.

The XOA and XOB inputs provide the input for the system clock.

These pins accept a reference clock in the 10 MHz to 600 MHz

range, or a 10 MHz to 50 MHz crystal connected directly across

the XOA and XOB inputs. The system clock provides the clocks

to the frequency monitors, the DPLL, and internal switching logic.

The AD9557 has two differential output drivers. Each driver has

a dedicated 10-bit programmable post divider. Each differential

driver is programmable either as a single differential or dual

single-ended CMOS output. The clock distribution section

operates at up to 1250 MHz.

In differential mode, the output drivers run on a 1.8 V power

supply to offer very high performance with minimal power

consumption. There are two differential modes: LVDS and 1.8 V

HSTL. In 1.8 V HSTL mode, the voltage swing is compatible

with LVPECL. If LVPECL signal levels are required, the designer

can ac-couple the AD9557 output and use Thevenin-equivalent

termination at the destination to drive the LVPECL inputs.

In single-ended mode, each differential output driver can

operate as two single-ended CMOS outputs. OUT0 supports

either 1.8 V or 3.3 V CMOS operation. OUT1 supports only

1.8 V operation.

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