AD9557SLASHPCBZ datasheet(49/92 Pages) AD

49 / 92 page

Data Sheet

AD9557

Rev. A | Page 49 of 92

Data Transfer Process

The master initiates data transfer by asserting a start condition.

This indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first) plus an R/W bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (0 =

write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

for data to be read from or written to it. If the R/W bit is 0, the

master (transmitter) writes to the slave device (receiver). If the

R/W bit is 1, the master (receiver) reads from the slave device

(transmitter).

The format for these commands is described in the Data

Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses: one data byte (eight bits) from either master (write mode)

or slave (read mode) followed by an acknowledge bit from the

receiving device. The number of bytes that can be transmitted

per transfer is unrestricted. In write mode, the first two data

bytes immediately after the slave address byte are the internal

memory (control registers) address bytes, with the high address

byte first. This addressing scheme gives a memory address of up

to 216 − 1 = 65,535. The data bytes after these two memory

address bytes are register data written to or read from the

control registers. In read mode, the data bytes after the slave

address byte are register data written to or read from the control

registers.

When all data bytes are read or written, stop conditions are

established. In write mode, the master (transmitter) asserts a

stop condition to end data transfer during the 10th clock pulse

following the acknowledge bit for the last data byte from the

slave device (receiver). In read mode, the master device

(receiver) receives the last data byte from the slave device

(transmitter) but does not pull SDA low during the ninth clock

pulse. This is known as a nonacknowledge bit. By receiving the

nonacknowledge bit, the slave device knows that the data

transfer is finished and enters idle mode. The master then takes

the data line low during the low period before the 10th clock

pulse, and high during the 10th clock pulse to assert a stop

condition.

A start condition can be used in place of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

3TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 52. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

3TO 7

ACK FROM

MASTER RECEIVER

NON-ACK FROM

MASTER RECEIVER

SDA

SCL

Figure 53. Data Transfer Process (Master Read Mode, 2-Byte Transfer)

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