AD9557SLASHPCBZ datasheet(44/92 Pages) AD

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AD9557

Data Sheet

Rev. A | Page 44 of 92

SERIAL CONTROL PORT

The AD9557 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The serial control port is compatible with most synchronous

transfer formats, including I2C, Motorola SPI, and Intel SSR

protocols. The serial control port allows read/write access to the

AD9557 register map.

In SPI mode, single or multiple byte transfers are supported.

The SPI port configuration is programmable via Register 0x0000.

This register is integrated into the SPI control logic rather than

in the register map and is distinct from the I2C Register 0x0000.

It is also inaccessible to the EEPROM controller.

Although the AD9557 supports both the SPI and I2C serial port

protocols, only one or the other is active following power-up

(as determined by the M0 and M1 multifunction pins during

the startup sequence). That is, the only way to change the serial

port protocol is to reset the device (or cycle the device power

supply).

SPI/I²C PORT SELECTION

Because the AD9557 supports both SPI and I2C protocols, the

active serial port protocol depends on the logic state of the

PINCONTROL, M1, and M0 pins. The PINCONTROL pin

must be low, and the state of the M0 and M1 pins determines

the I2C address, or if SPI mode is enabled. See Table 24 for the

I2C address assignments.

Table 24. SPI/I2C Serial Port Setup

SPI/I²C

Low

SPI

Low

Open

I²C, 1101000

Low

High

I²C, 1101001

Open

Low

I²C, 1101010

Open

I²C, 1101011

Open

High

I²C, 1101100

High

Low

I²C, 1101101

High

Open

I²C, 1101110

High

I²C, 1101111

SPI SERIAL PORT OPERATION

Pin Descriptions

The SCLK (serial clock) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 40 MHz.

The SDIO (serial data input/output) pin is a dual-purpose pin

and acts as either an input only (unidirectional mode) or as both

an input and an output (bidirectional mode). The AD9557

default SPI mode is bidirectional.

The SDO (serial data output) pin is useful only in unidirectional

I/O mode. It serves as the data output pin for read operations.

The CS (chip select) pin is an active low control that gates read

and write operations. This pin is internally connected to a 30 kΩ

pull-up resistor. When CS is high, the SDO and SDIO pins go

into a high impedance state.

SPI Mode Operation

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. By default, the

AD9557 uses the bidirectional MSB-first mode. The reason that

bidirectional is the default mode is so that the user can still

write to the device, if it is wired for unidirectional operation, to

switch to unidirectional mode.

Assertion (active low) of the CS pin initiates a write or read

operation to the

SPI port. For data transfers of three

bytes or fewer (excluding the instruction word), the device

supports the

AD9557

CS stalled high mode (see

). In this mode,

the

Table 25

CS pin can be temporarily deasserted on any byte boundary,

allowing time for the system controller to process the next byte.

CS can be deasserted only on byte boundaries, however. This

applies to both the instruction and data portions of the transfer.

During stall high periods, the serial control port state machine

enters a wait state until all data is sent. If the system controller

decides to abort a transfer midstream, the state machine must be

reset either by completing the transfer or by asserting the CS

pin for at least one complete SCLK cycle (but less than eight

SCLK cycles). Deasserting the CS pin on a nonbyte boundary

terminates the serial transfer and flushes the buffer.

In streaming mode (see Table 25), any number of data bytes can

be transferred in a continuous stream. The register address is

automatically incremented or decremented. CS must be deasserted

at the end of the last byte that is transferred, thereby ending the

stream mode.

Table 25. Byte Transfer Count

Bytes to Transfer

Streaming mode

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