AD9557SLASHPCBZ datasheet(33/92 Pages) AD

33 / 92 page

Data Sheet

AD9557

Rev. A | Page 33 of 92

SYSTEM CLOCK (SYSCLK)

SYSTEM CLOCK INPUTS

Functional Description

The SYSCLK circuit provides a low jitter, stable, high frequency

clock for use by the rest of the chip. The XOA and XOB pins

connect to the internal SYSCLK multiplier. The SYSCLK multiplier

can synthesize the system clock by connecting a crystal resonator

across the XOA and XOB input pins or by connecting a low

frequency clock source. The optimal signal for the system clock

input is either a crystal in the 50 MHz range or an ac-coupled

square wave with a 1 V p-p amplitude.

System Clock Period

For the AD9557 to accurately measure the frequency of incoming

reference signals, the user must enter the system clock period

into the nominal system clock period registers (Register 0x0103

to Register 0x0105). The SYSCLK period is entered in units of

nanoseconds (ns).

System Clock Details

There are two internal paths for the SYSCLK input signal: low

frequency non-xtal (LF) and crystal resonator (XTAL).

Using a TCXO for the system clock is a common use for the

LF path. Applications requiring DPLL loop bandwidths of less

than 50 Hz or high stability in holdover require a TCXO. As an

alternative to the 49.152 MHz crystal for these applications, the

AD9557 reference design uses a 19.2 MHz TCXO, which offers

excellent holdover stability and a good combination of low jitter

and low spurious content.

The 1.8 V differential receiver connected to the XOA and XOB pins

is self-biased to a dc level of ~1 V, and ac coupling is strongly

recommended. When a 3.3 V CMOS oscillator is in use, it is

important to use a voltage divider to reduce the input high voltage

to a maximum of 1.8 V. See Figure 34 for details on connecting

a 3.3 V CMOS TCXO to the system clock input.

The non-xtal input path permits the user to provide an LVPECL,

LVDS, 1.8 V CMOS, or sinusoidal low frequency clock for

multiplication by the integrated SYSCLK PLL. The LF path

handles input frequencies from 3.5 MHz up to 100 MHz.

However, when using a sinusoidal input signal, it is best to use

a frequency that is in excess of 20 MHz. Otherwise, the resulting

low slew rate can lead to substandard noise performance. Note

that the non-xtal path includes an optional 2× frequency multiplier

to double the rate at the input to the SYSCLK PLL and potentially

reduce the PLL in-band noise. However, to avoid exceeding the

maximum PFD rate of 150 MHz, the 2× frequency multiplier is

only for input frequencies that are below 75 MHz.

The non-xtal path also includes an input divider (M) that is

programmable for divide-by-1, -2, -4, or -8. The purpose of

the divider is to limit the frequency at the input to the PLL to

less than 150 MHz (the maximum PFD rate).

The XTAL path enables the connection of a crystal resonator

(typically 10 MHz to 50 MHz) across the XOA and XOB pins.

An internal amplifier provides the negative resistance required

to induce oscillation. The internal amplifier expects an AT cut,

fundamental mode crystal with a maximum motional resistance

of 100 Ω. The following crystals, listed in alphabetical order, may

meet these criteria. Analog Devices, Inc., does not guarantee their

operation with the AD9557, nor does Analog Devices endorse one

crystal supplier over another. The AD9557 reference design uses

a 49.152 MHz crystal, which is high performance, low spurious

content, and readily available.

•

AVX/Kyocera CX3225SB

•

ECS ECX-32

•

Epson/Toyocom TSX-3225

•

Fox FX3225BS

•

NDK NX3225SA

•

Siward SX-3225

•

Suntsu SCM10B48-49.152 MHz

SYSTEM CLOCK MULTIPLIER

The SYSCLK PLL multiplier is an integer-N design with an

integrated VCO. It provides a means to convert a low frequency

clock input to the desired system clock frequency, fSYS (750 MHz

to 805 MHz). The SYSCLK PLL multiplier accepts input signals

of between 3.5 MHz and 600 MHz, but frequencies that are in

excess of 150 MHz require the system clock P-divider to ensure

compliance with the maximum PFD rate (150 MHz). The PLL

contains a feedback divider (N) that is programmable for divide

values between 4 and 255.

Pdiv

sysclk

Ndiv

sysclk

OSC

SYS

where:

fOSC is the frequency at the XOA and XOB pins.

sysclk_Ndiv is the value stored in Register 0x0100.

sysclk_Pdiv is the system clock P divider that is determined by the

setting of Register 0x0101[2:1].

If the system clock doubler is used, the value of sysclk_Ndiv

should be half of its original value.

The system clock multiplier features a simple lock detector that

compares the time difference between the reference and feedback

edges. The most common cause of the SYSCLK multiplier not

locking is a non-50% duty cycle at the SYSCLK input while the

system clock doubler is enabled.

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