AD9557SLASHPCBZ datasheet(70/92 Pages) AD

70 / 92 page

AD9557

Data Sheet

Rev. A | Page 70 of 92

Table 56. DPLL Frequency Clamp

Address

Bits

Bit Name

Description

0x0306

[7:0]

Lower limit pull-in range bits[7:0]

Default: 0x51

0x0307

[7:0]

Lower limit of pull-in range (expressed as

a 20-bit frequency tuning word)

Lower limit pull-in range bits[15:8]

Default: 0xB8

0x0308

[7:4]

Reserved

Default: 0x0

[3:0]

Lower limit of pull-in range

Lower limit pull-in range bits[19:16]

Default: 0x2

0x0309

[7:0]

Upper limit pull-in range bits[7:0]

Default: 0x3E

0x030A

[7:0]

Upper limit of pull-in range (expressed as

a 20-bit frequency tuning word)

Upper limit pull-in range bits[15:8]

Default: 0x0A

0x030B

[7:4]

Reserved

Default: 0x0

[3:0]

Upper limit of pull-in range

Upper limit pull-in range bits[19:16]

Default: 0xB

Table 57. Fixed Closed-Loop Phase Lock Offset

Address

Bits

Bit Name

Description

0x030C

[7:0]

Fixed phase lock offset bits[7:0]

Default: 0x00

0x030D

[7:0]

Fixed phase lock offset bits[15:8]

Default 0x00

0x030E

[7:0]

Fixed phase lock offset (signed; ps)

Fixed phase lock offset bits[23:16]

Default: 0x00

0x030F

[7:6]

Reserved

Reserved; default: 0x0

[5:0]

Fixed phase lock offset (signed; ps)

Fixed phase lock offset bits[29:24]

Default: 0x00

Table 58. Incremental Closed-Loop Phase Lock Offset Step Size1

Address

Bits

Bit Name

Description

0x0310

[7:0]

Incremental phase lock offset step size bits[7:0].

Default: 0x00.

This controls the static phase offset of the DPLL while it is locked.

0x0311

[7:0]

Incremental phase lock offset step size (ps)

Incremental phase lock offset step size bits[15:8] Default: 0x00.

This controls the static phase offset of the DPLL while it is locked.

1 Note that the default incremental closed-loop phase lock offset step size value is 0x0000 = 0 (0 ns).

Table 59. Phase Slew Rate Limit

Address

Bits

Bit Name

Description

0x0312

[7:0]

Phase slew rate limit bits[7:0].

Default: 0x00.

This register controls the maximum allowable phase slewing during

transients and reference switching.

The default phase slew rate limit is 0, or disabled. Minimum useful value is

310 μs/sec.

0x0313

[7:0]

Phase slew rate limit (μs/sec)

Phase slew rate limit bits[15:8] .

Default: 0x00.

AD9557/PCBZ датащи(PDF) 70 Page - Analog Devices

AD9557/PCBZ датащи(HTML) 70 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL