AD9557SLASHPCBZ datasheet(77/92 Pages) AD

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Data Sheet

AD9557

Rev. A | Page 77 of 92

DPLL PROFILE REGISTERS (REGISTER 0x0700 TO REGISTER 0x0766)

Note that the default value of the REFA profile is as follows: input frequency = 19.44 MHz, output frequency = 622.08 MHz/155.52 MHz,

loop bandwidth = 400 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.

The default value of REFB profile is as follows: input frequency = 8 kHz, output frequency = 622.08 MHz/155.52 MHz, loop bandwidth =

100 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.

REFA Profile (Register 0x0700 to Register 0x0726)

Table 75. Reference Period—REFA Profile

Address

Bits

Bit Name

Description

0x0700

[7:0]

Nominal reference period bits[7:0] (default: 0xC9)

0x0701

[7:0]

Nominal reference period bits[15:8] (default: 0xEA)

0x0702

[7:0]

Nominal reference period bits[23:16] (default: 0x10)

0x0703

[7:0]

Nominal reference period bits[31:24] (default: 0x03)

0x0704

[7:0]

Nominal reference period (fs)

Nominal reference period bits[39:32] (default: 0x00)

Default for Register 0x0700 to Register 0x0704 = 0x000310EAC9 = 51.44 ns (1/19.44 MHz)

Table 76. Reference Period Tolerance—REFA Profile

Address

Bits

Bit Name

Description

0x0705

[7:0]

Input reference frequency monitor inner tolerance bits [7:0] (default: 0x14).

0x0706

[7:0]

Inner tolerance

Input reference frequency monitor inner tolerance bit [15:8] (default: 0x00).

[7:4]

Reserved

Reserved.

0x0707

[3:0]

Inner tolerance

Input reference frequency monitor inner tolerance bits[19:16].

Default for Register 0x0705 to Register 0x0707 = 0x000014 = 20 (5% or 50,000 ppm).

The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;

an SMC clock requires an outer tolerance of ±48 ppm.

The allowable range for the inner tolerance is 0x0000A (10%) to 0xFFFFF (1 ppm).

The tolerance of the input frequency monitor is only as accurate as the system clock

frequency.

0x0708

[7:0]

Input reference frequency monitor outer tolerance bits [7:0] (default: 0x0A).

0x0709

[7:0]

Outer tolerance

Input reference frequency monitor outer tolerance bits[15:8] (default: 0x00).

[7:4]

Reserved

Reserved.

0x070A

[3:0]

Outer tolerance

Input reference frequency monitor outer tolerance bits[19:16] .

Default for Register 0x0708 to Register 0x070A = 0x00000A = 10 (10% or 100,000 ppm).

The Stratum 3 clock requires an inner tolerance of ±9.2 ppm and outer tolerance of

±12 ppm; an SMC clock requires an outer tolerance of ±48 ppm.

The outer tolerance register setting should always be smaller than the inner tolerance.

Table 77. Reference Validation Timer—REFA Profile

Address

Bits

Bit Name

Description

0x070B

[7:0]

Validation timer bits[7:0] (default: 0x0A).

This is the amount of time a reference input must be valid before it is declared valid by

the reference input monitor (default: 10 ms).

0x070C

[7:0]

Validation timer (ms)

Validation timer bits[15:8] (default: 0x00).

Table 78. Reserved Register

Address

Bits

Bit Name

Description

0x070D

[7:0]

Reserved

Default: 0x00

Table 79. DPLL Base Loop Filter Selection—REFA Profile

Address

Bits

Bit Name

Description

[7:1]

Reserved

Default: 0x00

0x070E

Sel high PM base loop filter

0 = base loop filter with normal (70°) phase margin (default)

1 = base loop filter with high (88.5°) phase margin

(≤0.1 dB peaking in the closed-loop transfer function for loop bandwidths ≤ 2 kHz;

setting this bit is also recommended for loop bandwidths > 2kHz)

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