AD9557SLASHPCBZ datasheet(51/92 Pages) AD

51 / 92 page

Data Sheet

AD9557

Rev. A | Page 51 of 92

PROGRAMMING THE I/O REGISTERS

The register map spans an address range from 0x0000 through

0x0E3C. Each address provides access to 1 byte (eight bits)

of data. Each individual register is identified by its four-digit

hexadecimal address (for example, Register 0x0A10). In some

cases, a group of addresses collectively defines a register.

In general, when a group of registers defines a control parameter,

the LSB of the value resides in the D0 position of the register

with the lowest address. The bit weight increases right to left,

from the lowest register address to the highest register address.

Note that the EEPROM storage sequence registers (Address 0x0E10

to Address 0x0E3C) are an exception to the above convention (see

the EEPROM Instructions section).

BUFFERED/ACTIVE REGISTERS

There are two copies of most registers: buffered and active. The

value in the active registers is the one that is in use. The buffered

registers are the ones that take effect the next time the user

writes 0x01 to the I/O update register (Register 0x0005).

Buffering the registers allows the user to update a group of

registers (like the digital loop filter coefficients) at the same

time, which avoids the potential of unpredictable behavior in

the part. Registers with an L in the option column are live,

meaning that they take effect the moment the serial port

transfers that data byte.

AUTOCLEAR REGISTERS

An A in the option column of the register map identifies an

autoclear register. Typically, the active value for an autoclear

by the internal device logic upon completion of the prescribed

action.

Read and write access to the register map may be restricted

depending on the register in question, the source and direction

of access, and the current state of the device. Each register can

be classified into one or more access types. When more than

one type applies, the most restrictive condition is the one that

applies.

Whenever access is denied to a register, all attempts to read the

are ignored. Access to nonexistent registers is handled in the

same way as for a denied register.

Regular Access

Registers with regular access do not fall into any other category.

Both read and write access to registers of this type can be from

either the serial ports or the EEPROM controller. However, only

one of these sources can have access to a register at any given

time (access is mutually exclusive). When the EEPROM controller

is active, in either load or store mode, it has exclusive access to

these registers.

Read-Only Access

An R in the option column of the register map identifies read-

only registers. Access is available at all times, including when

the EEPROM controller is active. Note that read-only registers

(R) are inaccessible to the EEPROM, as well.

Exclusion from EEPROM Access

An E in the option column of the register map identifies a

That is, the contents of this type of register cannot be

transferred directly to the EEPROM or vice versa. Note that

read-only registers (R) are inaccessible to the EEPROM, as well.

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