AD9557SLASHPCBZ datasheet(66/92 Pages) AD

66 / 92 page

AD9557

Data Sheet

Rev. A | Page 66 of 92

SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)

Table 42. System Clock PLL Feedback Divider (N3 Divider)

Address

Bits

Bit Name

Description

0x0100

[7:0]

SYSCLK N3 divider

System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08).

Table 43. SYSCLK Configuration

Address

Bits

Bit Name

Description

[7:5]

Reserved

Reserved.

Load from ROM (reserved)

This reserved bit has no function.

0 (default) = power-on default and ROM not loaded.

1 = ROM values are loaded into the register space.

SYSCLK XTAL enable

Enables the crystal maintaining amplifier for the system clock input.

1 (default) = crystal mode (crystal maintaining amplifier enabled).

0 = external XO or other system clock source.

[2:1]

SYSCLK P divider

System clock input divider.

00 (default) = 1.

01 = 2.

10 = 4.

11 = 8.

0x0101

SYSCLK doubler enable

Enable clock doubler on system clock input to reduce noise.

0 = disable.

1 (default) = enable.

Table 44. Nominal System Clock Period

Address

Bits

Bit Name

Description

0x0103

[7:0]

System clock period, Bits[7:0].

Default: 0x0E.

0x0104

[7:0]

Nominal system clock period (fs)

System clock period, Bits[15:8].

Default: 0x67.

[7:5]

Reserved

Reserved.

0x0105

[4:0]

Nominal system clock period (fs)

System clock period, Bits[20:16].

Default: 0x13.

Table 45. System Clock Stability Period

Address

Bits

Bit Name

Description

0x0106

[7:0]

System clock period, Bits[7:0].

Default: 0x32 (0x000032 = 50 ms).

0x0107

[7:0]

System clock stability period (ms)

System clock period, Bits[15:8].

Default: 0x00.

[7:5]

Reserved

Reserved.

Reset SYSCLK stability timer

This autoclearing bit resets the system clock stability timer.

0x0108

[3:0]

System clock stability period

System clock period, Bits[19:16].

Default: 0x00.

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