AD9557SLASHPCBZ datasheet(85/92 Pages) AD

85 / 92 page

Data Sheet

AD9557

Rev. A | Page 85 of 92

DPLL Status, Input Reference Status, Holdover History, and DPLL Lock Detect Tub Levels (Register 0x0D08 to Register 0x0D14)

Table 105. DPLL Status

Address

Bits

Bit Name

Description

Reserved

Offset slew limiting

The current closed-loop phase offset is rate limited

Frequency lock

The DPLL has achieved frequency lock

Phase lock

The DPLL has achieved phase lock

Loop switching

The DPLL is in the process of a reference switchover

Holdover

The DPLL is in holdover mode

Active

The DPLL is active (that is, operating in a closed-loop condition)

0x0D08

Freerun

The DPLL is free run (that is, operating in an open-loop condition)

[7:6]

Reserved

Default: 0b

Frequency clamped

The upper or lower frequency tuning word clamp is in effect

History available

There is sufficient tuning word history available for holdover operation

[3:2]

Active reference priority

Priority value of the currently active reference

00 = highest priority

…

11 = lowest priority

0x0D09

Reserved

Default: 0b

Current active reference

Index of the currently active reference

0 = Reference A

1 = Reference B

Table 106. Reserved Register

Address

Bits

Bit Name

Description

0x0D0A

[7:0]

Reserved

Table 107. Input Reference Status

Address

Bits

Bit Name

Description

B valid

REFB is valid for use (it is unfaulted, and its validation timer has expired).

B fault

REFB is not valid for use.

B fast

This bit indicates that the frequency of REFB is higher than allowed by its profile settings.

B slow

This bit indicates that the frequency of REFB is lower than allowed by its profile settings.

A valid

REFA is valid for use (it is unfaulted and its validation timer has expired).

A fault

REFA is not valid for use.

A fast

This bit indicates that the frequency of REFA is higher than allowed by its profile settings.

0x0D0B

A slow

This bit indicates that the frequency of REFA is lower than allowed by its profile settings.

0x0D0C

[7:0]

Reserved

Reserved.

Table 108. Holdover History1

Address

Bits

Bit Name

Description

0x0D0D

[7:0]

Tuning word readback bits[7:0]

0x0D0E

[7:0]

Tuning word readback bits[15:8]

0x0D0F

[7:0]

Tuning word readback bits[23:9]

0x0D10

[7:0]

Tuning word readback

Tuning word readback bits[31:24]

1 Note that these registers contain the current 30-bit DCO frequency tuning word that is generated by the tuning word history logic.

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