AD9557SLASHPCBZ datasheet(67/92 Pages) AD

67 / 92 page

Data Sheet

AD9557

Rev. A | Page 67 of 92

GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214)

Multifunction Pin Control (M3 to M0) and IRQ Pin Control (Register 0x0200 to Register 0x0209)

Note that the default setting for the M3 to M0 multifunction pins and the IRQ pin is that of a 3-level logic input at startup. Setting Bit 1 in

Table 46. Multifunction Pins (M0 to M3) Control

Address

Bits

Bit Name

Description

0x0200

[7:1]

Reserved

Enable M pins and IRQ pin function

0 (default) = disables the function of the M pins and the IRQ pin control register

(Address 0x0201 to Address 0x0209); the M pins and IRQ pin are in 3-level logic

input state.

1 = the M pins and IRQ pin are out of 3-level logic input state and enable the

binary function of the M pins and the IRQ pin control registers (Address 0x0201

to Address 0x0209).

0x0201

M0 output/input

In/out control for M0 pin.

0 = input (2-level logic control pin).

1 (default) = output (2-level logic status pin).

[6:0]

Function

See Table 124 and Table 125. Default: 0xB0 = REFA valid.

0x0202

M1 output/input

In/out control for M1 pin (same as M0).

[6:0]

Function

See Table 124 and Table 125. Default: 0xB1 = REFB valid.

0x0203

M2 output/input

In/out control for M2 pin (same as M0).

[6:0]

Function

See Table 124 and Table 125. Default: 0xC0 = REFA active.

0x0204

M3 output/input

In/out control for M3 pin (same as M0).

[6:0]

Function

See Table 124 and Table 125. Default: 0xC1 = REFB active.

0x0205

[7:0]

Reserved

Reserved.

0x0206

[7:0]

Reserved

Reserved.

0x0207

[7:0]

Reserved

Reserved.

0x0208

[7:0]

Reserved

Reserved.

Table 47. IRQ Pin Output Mode

Address

Bits

Bit Name

Description

0x0209

[7:5]

Reserved

[4:3]

Status signal at IRQ pin[1:0]

This selection is valid only when Address 0x0209[2] = 1

00 = DPLL phase locked

01 = DPLL frequency locked

10 = system clock PLL locked

11 (default) = (DPLL phase locked) AND (system clock PLL locked) AND (APLL locked)

Use IRQ pin for status signal

0 = uses IRQ pin to monitor IRQ event

1 (default) = uses IRQ pin to monitor internal status signals

[1:0]

IRQ pin driver type

Select the output mode of the IRQ pin

00 = NMOS, open drain (requires an external pull-up resistor)

01 = PMOS, open drain (requires an external pull-down resistor)

10 = CMOS, active high

11 (default) = CMOS, active low

AD9557/PCBZ датащи(PDF) 67 Page - Analog Devices

AD9557/PCBZ датащи(HTML) 67 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL