AD9557SLASHPCBZ datasheet(7/92 Pages) AD

7 / 92 page

Data Sheet

AD9557

Rev. A | Page 7 of 92

REFERENCE INPUTS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

Sinusoidal Input

750

MHz

LVPECL Input

0.002

1250

MHz

The reference input divide-by-2 block must be engaged

for fIN > 705 MHz

LVDS Input

0.002

750

MHz

The reference input divide-by-2 block must be engaged

for fIN > 705 MHz

Minimum Input Slew Rate

V/μs

Minimum limit imposed for jitter performance

Common-Mode Input Voltage

AC-Coupled

1.9

2.1

Internally generated

DC-Coupled

1.0

2.4

Differential Input Voltage Sensitivity

Minimum differential voltage across pins is required to

ensure switching between logic levels; instantaneous

voltage on either pin must not exceed the supply rails

fIN < 800 MHz

240

fIN = 800 to 1050 MHz

320

fIN = 1050 to 1250 MHz

400

Differential Input Voltage Hysteresis

100

Input Resistance

kΩ

Input Capacitance

Minimum Pulse Width High

LVPECL

390

LVDS

640

Minimum Pulse Width Low

LVPECL

390

LVDS

640

SINGLE-ENDED OPERATION

Frequency Range (CMOS)

0.002

300

MHz

Minimum Input Slew Rate

V/μs

Minimum limit imposed for jitter performance

Input Voltage High (VIH)

1.2 V to 1.5 V Threshold Setting

1.0

1.8 V to 2.5 V Threshold Setting

1.4

3.0 V to 3.3 V Threshold Setting

2.0

Input Voltage Low (VIL)

1.2 V to 1.5 V Threshold Setting

0.35

1.8 V to 2.5 V Threshold Setting

0.5

3.0 V to 3.3 V Threshold Setting

1.0

Input Resistance

kΩ

Input Capacitance

Minimum Pulse Width High

1.5

Minimum Pulse Width Low

1.5

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