AD9557SLASHPCBZ datasheet(11/92 Pages) AD

11 / 92 page

Data Sheet

AD9557

Rev. A | Page 11 of 92

DIGITAL PLL

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL PLL

Phase-Frequency Detector (PFD)

Input Frequency Range

100

kHz

Loop Bandwidth

0.1

2000

Programmable design parameter

Phase Margin

Degrees

Programmable design parameter

Closed-Loop Peaking

<0.1

Programmable design parameter; part can be

programmed for <0.1 dB peaking in accordance with

Telcordia GR-253 jitter transfer

Reference Input (R) Division Factor

220

1, 2, …, 1,048,576

Integer Feedback (N1) Division Factor

180

217

180, 181, …, 131,072

Fractional Feedback Divide Ratio

0.999

Maximum value: 16,777,215/16,777,216

DIGITAL PLL LOCK DETECTION

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range

0.001

65.5

Threshold Resolution

FREQUENCY LOCK DETECTOR

Threshold Programming Range

0.001

16,700

Reference-to-feedback period difference

Threshold Resolution

HOLDOVER SPECIFICATIONS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

<0.01

ppm

Excludes frequency drift of SYSCLK source; excludes

frequency drift of input reference prior to entering

holdover; compliant with GR-1244 Stratum 3

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