AD9557SLASHPCBZ datasheet(17/92 Pages) AD

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Data Sheet

AD9557

Rev. A | Page 17 of 92

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).

IRQ

SCLK/SCL

SDIO/SDA

SDO

DVDD

AVDD

XOA

XOB

AVDD

23 AVDD

24 AVDD

25 RESET

26 PINCONTROL

27 SYNC

28 REFA

29 REFA

30 DVDD3

22 AVDD

21 LF_VCO2

TOP VIEW

(Not to Scale)

AD9557

Figure 2. Pin Configuration

Table 20. Pin Function Descriptions

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

IRQ

3.3 V CMOS

Interrupt Request Line.

SCLK/SCL

3.3 V CMOS

Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming.

Serial Clock Pin (SCL) in I2C Mode.

SDIO/SDA

I/O

3.3 V CMOS

Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI

mode, data is written via this pin. In 3-wire mode, both data reads and writes

occur on this pin. There is no internal pull-up/pull-down resistor on this pin.

Serial Data Pin (SDA) in I2C Mode.

SDO

3.3 V CMOS

Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal

pull-up/pull-down resistor on this pin. This pin is high impedance in the default

3-wire mode.

3.3 V CMOS

Chip Select (SPI), Active Low. When programming a device, this pin must be held

low. In systems where more than one AD9557 is present, this pin enables

individual programming of each AD9557. This pin has an internal 10 kΩ pull-up

resistor.

6, 34, 35

DVDD

Power

1.8 V Digital Supply.

7, 10, 22,

23, 24

AVDD

Power

1.8 V Analog Power Supply.

XOA

Differential

input

System Clock Input. XOA contains internal dc biasing and should be ac-coupled

with a 0.01 μF capacitor, except when using a crystal, in which case connect the

crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can

introduce a spur if the duty cycle is not 50%. When using XOA as a single-ended

input, connect a 0.01 μF capacitor from XOB to ground.

XOB

Differential

input

Complementary System Clock Input. Complementary signal to XOA. XOB contains

internal dc biasing and should be ac-coupled with a 0.01 μF capacitor, except

when using a crystal, in which case connect the crystal across XOA and XOB.

11, 17, 18

AVDD

Power

1.8 V Analog (Output Divider and Drivers) Power Supply.

OUT1

HSTL, LVDS, or

1.8 V CMOS

Complementary Output 1. This output can be configured as HSTL, LVDS, or

single-ended 1.8 V CMOS.

OUT1

HSTL, LVDS, or

1.8 V CMOS

Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations

section.

14, 19

AVDD3

Power

3.3 V Analog Power Supply.

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