MPF0900AMBA2ES datasheet(138/205 Pages) NXP

138 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

aaa-056078

Time

10 %

fosc

0.5 %

resolution

Figure 36. Pseudo-random modulation

13.4.2 Clock synchronization

The FSYNC pin is a bidirectional clock pin used to enable clock synchronization with one or more external

devices. The pin is suitable for 1.8 V or 3.3 V level signals.

The mode of operation of the FSYNC pin is set on OTP via the OTP_FSYNC_MODE bits, and cannot be

changed during the system operation.

OTP_FSYNC_MODE

FSYNC operating mode

SYNCOUT mode

SYNCIN Mode

Table 185. FSYNC mode selection bit

13.4.2.1 SYNCOUT mode

When the FSYNC pin is operating in SYNCOUT mode, the pin provides a signal toggling with the same

frequency as the switching regulators (HFREQ_CLK / 8). In this mode, the device always uses the internal high-

frequency clock to generate the switching frequency for the switching regulators.

The FSYNCOUT_EN bit is used to enable or disable the output frequency in the FSYNC pin. By default, the

output frequency is disabled, and the MCU must enable it during the configuration phase.

FSYNCOUT_EN

FSYNC output frequency

Disabled

Enabled

Table 186. Enabling FSYNC output frequency enable bit

13.4.2.2 SYNCIN mode

When the FSYNC pin is operating in SYNCIN mode, an external clock can be fed via the FSYNC pin to

synchronize the switching regulators to the external clock. When the external clock synchronization is enabled,

the system is expected to operate the switching regulators in PWM mode to ensure clock synchronization.

When the external clock synchronization is enabled, the internal PLL is enabled to generate the switching

regulator frequency from either the internal high frequency clock or the external frequency at the FSYNC pin,

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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