MPF0900AMBA2ES datasheet(146/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

14.1 Output voltage monitoring

The PF09 is intended to operate as the main safety controller for the full power management architecture,

providing high precision OV/UV monitoring during the RUN and Monitored STANDBY states for the PF09

system regulators, as well as external regulators supplied by one or more companion PMICs.

The OV/UV monitoring circuits implement a dedicated bandgap reference which is fully independent from the

bandgap reference used for the voltage generation.

Safety OV/UV monitoring is performed on the following regulators:

• Switch mode power supplies (SMPS): SW1, SW2, SW3, SW4, SW5

• Linear regulators (LDO): LDO1, LDO2, LDO3, VAON

External voltage monitoring is performed via the two dedicated external VMON pins.

• VMON1

• VMON2

Additional external voltage monitoring pins are available in the LDO2 and LDO3 if the regulators are not

required in the system.

• VLDO2MON (LDO2OUT pin)

• VLDO3MON (LDO3OUT pin)

Refer to section 17.3 Voltage Monitoring for operational details of the safety-related VMON blocks.

Voltage monitoring of the VAON regulator in the Low-power modes (OFF and STANDBY states) is not

considered to be a safety-related mechanism, therefore the undervoltage detection in such scenarios is

designed to prioritize power consumption over physical independence of the voltage reference between the

regulator and the voltage monitor.

14.1.1 Voltage monitoring during a pin disconnection

The switching regulators and LDOs are provided with a pin-lift mechanism to detect a random pin disconnection

that could potentially lead to an unsafe/undetectable condition, resulting in a violation of the safety goal.

When the VAON operates as an always-on regulator with very low quiescent current, this rail is intended to

supply the low-level voltage domain in the MCU in charge of communicating and interfacing with the PF09

device. It is assumed a pin disconnection in the VAON output will cause the MCU to become unresponsive, and

such a fault will be detected by other mechanisms, therefore a pin-lift feature is not needed in the VAON.

14.1.1.1 Switching regulators FB disconnection

Each switching regulator is provided with an internal weak pullup resistor to VIN at its respective SWxFB pad, to

ensure the VMON is able to perform a safe reaction when the regulation is operating in PWM mode.

A pullup on the FB node will force the VMON into to an OV condition, while the error amplifier will try to lower

the output voltage by reducing the PWM, resulting in an incorrect OV fault detection but safe reaction to an FB

pin disconnection.

It is assumed the PFM mode is intended to be used during low-power STANDBY mode, which is considered

a safe state with no critical activity. In these scenarios, the internal pullup resistor will be disabled in the PFM

mode to ensure proper operation of the PFM control loop.

14.1.1.2 LDO regulators output disconnection

The LDOs are provided with an internal mechanism to detect a real-time pin disconnection during normal

operation. A current source injects small amounts of current with a frequency wide enough to cause a pin

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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