ADFS7124-8BBCPZ datasheet(15/93 Pages) AD

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Data Sheet

ADFS7124-8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 15 of 93

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can be anywhere

between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) − REFIN1(−)) is 2.5 V, but the device functions with a

reference from 0.5 V to AVDD.

REFIN1(−)

Negative Reference Input. This reference input can be anywhere between AVSS and AVDD – 0.5 V.

AIN8/IOUT/VBIAS

Analog Input 8/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN9/IOUT/VBIAS

Analog Input 9/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN10/IOUT/VBIAS

Analog Input 10/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN11/IOUT/VBIAS

Analog Input 11/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN12/IOUT/VBIAS

Analog Input 12/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN13/IOUT/VBIAS

Analog Input 13/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through the configuration

registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the internal programmable

excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin.

AIN14/IOUT/VBIAS/

REFIN2(+)

Analog Input 14/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively,

the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to

this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as

a positive reference input for REFIN2(±). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference

voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

AIN15/IOUT/VBIAS/

REFIN2(−)

Analog Input 15/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This input pin is configured

through the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input. Alternatively, the

internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this

output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as the

negative reference input for REFIN2(±). This reference input can be anywhere between AVSS and AVDD – 0.5 V.

REFOUT

Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

AVSS

Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS must be between 2.7

V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power mode. AVSS can be taken below 0 V to provide a

dual power supply to the ADFS7124-8. For example, AVSS can be tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V

supply to the ADC.

REGCAPA

Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 µF capacitor.

PSW

Low-Side Power Switch to AVSS.

AVDD

Analog Supply Voltage, Relative to AVSS.

SYNC

Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog modulators when using a

number of ADFS7124-8 devices. When SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control

logic are reset, and the analog modulator is held in a reset state. SYNC does not affect the digital interface but does reset RDY to a

high state if it is low.

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