ADFS7124-8BBCPZ datasheet(52/93 Pages) AD

52 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 52 of 93

Continuous Read Mode

In the continuous read mode, it is not required to write to the com-

munications register before reading ADC data; apply the required

number of SCLKs after DOUT/RDY goes low to indicate the end

of a conversion. When the conversion is read, DOUT/RDY returns

high until the next conversion is available. In this mode, the data

can be read only once. Ensure that the data-word is read before

the next conversion is complete. If the conversion is not read before

the completion of the next conversion, or if insufficient serial clocks

are applied to the ADFS7124-8 to read the word, the serial output

new conversion is placed in the output serial register. The ADC

must be configured for the continuous conversion mode to use the

continuous read mode.

To enable the continuous read mode, set the CONT_READ bit in

the ADC_CONTROL register. When this bit is set, the only serial

interface operations possible are reads from the data register. To

exit the continuous read mode, write a read data command (0x42)

while the DOUT/RDY pin is low. Alternatively, apply a software

reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the

ADC and all register contents. These are the only commands that

the interface recognizes after it is placed in the continuous read

mode. DIN must be held low in the continuous read mode until an

instruction is to be written to the device.

If multiple ADC channels are enabled, each channel is output in

turn, with the status bits being appended to the data if DATA_

STATUS is set in the ADC_CONTROL register. The status register

indicates the channel to which the conversion corresponds.

DATA_STATUS

The contents of the status register can be appended to each

conversion on the ADFS7124-8. This is a useful function if several

channels are enabled. Each time a conversion is output, the con-

tents of the status register are appended. The four LSBs of the sta-

tus register indicate to which channel the conversion corresponds.

In addition, determine if any errors are being flagged through the

ERROR_FLAG bit. To append the status register contents to every

conversion, the DATA_STATUS bit in the ADC_CONTROL register

is set to 1.

SERIAL INTERFACE RESET (DOUT_RDY_DEL

AND CS_EN BITS)

The instant at which the DOUT/RDY pin changes from being a

DOUT pin to a RDY pin is programmable on the ADFS7124-8. By

default, the DOUT/RDY pin changes functionality after a period of

time following the last SCLK rising edge, the SCLK edge on which

the LSB is read by the processor. This time is 10 ns minimum

by default and, by setting the DOUT_RDY_DEL bit in the ADC_

CONTROL register to 1, can be extended to 110 ns minimum.

By setting the CS_EN bit in the ADC_CONTROL register to 1, the

DOUT/RDY pin continues to output the LSB of the register being

read until CS is taken high. This configuration is useful if the CS

signal is used to frame all read operations. If CS is not used to

frame all read operations, set CS_EN to 0 so that DOUT/RDY

changes functionality following the last SCLK edge in the read

operation.

CS_EN must be set to 1 and the CS signal must be used to

frame all read and write operations when the SPI_READ_ERR,

SPI_WRITE_ERR, and SPI_SCLK_CNT_ERR diagnostic functions

are enabled.

The serial interface is always reset on the CS rising edge, that is,

the interface is reset to a known state whereby it awaits a write to

the communications register. Therefore, if a read or write operation

is performed by performing multiple 8-bit data transfers, CS must

be held low until the all bits are transferred.

RESET

The circuitry and serial interface of the ADFS7124-8 can be reset

by writing 64 consecutive 1s to the device. This resets the logic,

digital filter, and analog modulator, and all on-chip registers are

reset to their default values. A reset is automatically performed on

power-up. A reset requires a time of 90 MCLK cycles. A reset is

useful if the serial interface becomes asynchronous due to noise on

the SCLK line.

CALIBRATION

The ADFS7124-8 provides four calibration modes to eliminate the

offset and gain errors on a per setup basis:

►

Internal zero-scale calibration mode

►

Internal full-scale calibration mode

►

System zero-scale calibration mode

►

System full-scale calibration mode

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The default value of the offset register is 0x800000, and the nomi-

nal value of the gain register is 0x5XXXXX. The calibration range of

the ADC gain is from 0.4 × VREF/gain to 1.05 × VREF/gain.

The following equations show the calculations that are used in each

calibration mode. In the unipolar mode, the ideal relationship (that

is, not taking into account the ADC gain error and offset error) is as

follows:

Data=0.75×VIN

VREF ×223− Offset−0x800000 ×

Gain

0x400000×2

(1)

In the bipolar mode, the ideal relationship (that is, not taking into

account the ADC gain error and offset error) is as follows:

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