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ADFS7124-8BBCPZ датащи(PDF) 8 Page - Analog Devices

номер детали ADFS7124-8BBCPZ
подробное описание детали  8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
PDF  93 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADFS7124-8BBCPZ датащи(HTML) 8 Page - Analog Devices

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Data Sheet
ADFS7124-8
SPECIFICATIONS
analog.com
Rev. 0 | 8 of 93
Table 2. Specifications (Continued)
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
0.35 × IOVDD
V
1.9 V ≤ IOVDD < 2.3 V
0.7
V
2.3 V ≤ IOVDD ≤ 3.6 V
High, VINH
0.7 × IOVDD
V
1.65 V ≤ IOVDD < 1.9 V
0.65 × IOVDD
V
1.9 V ≤ IOVDD < 2.3 V
1.7
V
2.3 V ≤ IOVDD < 2.7 V
2
V
2.7 V ≤ IOVDD ≤ 3.6 V
Hysteresis
0.2
0.6
V
1.65 V ≤ IOVDD ≤ 3.6 V
Input Currents
−1
+1
µA
VIN = IOVDD or GND
Input Capacitance
10
pF
All digital inputs
LOGIC OUTPUTS (INCLUDING CLK)
Output Voltage2
High, VOH
IOVDD − 0.35
V
ISOURCE = 100 µA
Low, VOL
0.4
V
ISINK = 100 µA
Floating State Leakage Current
−1
+1
µA
Floating State Output Capacitance
10
pF
Data Output Coding
Offset binary
SYSTEM CALIBRATION2
Calibration Limit
Full-Scale
1.05 × FS
V
Zero-Scale
−1.05 × FS
V
Input Span
0.8 × FS
2.1 × FS
V
POWER SUPPLY VOLTAGES FOR ALL POWER
MODES
AVDD to AVSS
Low Power Mode
2.7
3.6
V
Mid Power Mode
2.7
3.6
V
Full Power Mode
2.9
3.6
V
IOVDD to GND
1.65
3.6
V
AVSS to GND
−1.8
0
V
IOVDD to AVSS
5.4
V
POWER SUPPLY CURRENTS11, 13
IAVDD, External Reference
Low Power Mode
Gain = 12
125
140
µA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
15
25
µA
Gain = 2 to 8
205
250
µA
Gain = 16 to 128
235
300
µA
IAVDD Increase per Reference Buffer2
10
20
µA
All gains
Mid Power Mode
Gain = 12
150
170
µA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
30
40
µA
Gain = 2 to 8
275
345
µA
Gain = 16 to 128
330
430
µA
IAVDD Increase per Reference Buffer2
20
30
µA
All gains
Full Power Mode
Gain = 12
315
350
µA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
90
135
µA
Gain = 2 to 8
660
830
µA
Gain = 16 to 128
875
1200
µA



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