ADFS7124-8BBCPZ datasheet(56/93 Pages) AD

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Data Sheet

ADFS7124-8

DIGITAL FILTER

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Rev. 0 | 56 of 93

Sinc4 Zero Latency

Zero latency is enabled by setting the SINGLE_CYCLE bit in the

filter register to 1. With zero latency, the conversion time when

continuously converting on a single channel approximately equals

the settling time. The benefit of this mode is that a similar period

of time elapses between all conversions irrespective of whether the

conversions occur on one channel or whether several channels are

used. When the analog input is continuously sampled on a single

channel, the output data rate equals:

fADC = fCLK/(4 × 32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controller clock frequency.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the setup

filter register.

When selecting another channel, there is an extra delay in the first

conversion of:

Dead Time/fCLK

where, Dead Time = 61 when FS[10:0] = 1 and 95 when FS[10:0] >

At low output data rates, this extra delay has little impact on the

value of the settling time. However, at high output data rates, the

delay must be considered. Table 56 summarizes the output data

rate when continuously converting on a single channel and the

settling time when switching between channels for a sample of

FS[10:0] values.

When switching between channels, the ADFS7124-8 allows the

complete settling time to generate the first conversion after the

channel change. Therefore, the ADC automatically operates in

zero latency mode when several channels are enabled (setting the

SINGLE_CYCLE bit has no benefits).

Table 56. Examples of Output Data Rates and the Corresponding Settling

Times for the Sinc4 Filter (Zero Latency)

Power Mode

FS[10:0]

Output Data Rate

(SPS)

Settling Time

(ms)

Full Power (fCLK =

614.4 kHz)

1920

2.5

400.15

384

12.5

80.15

320

66.82

Mid Power (fCLK =

153.6 kHz)

480

2.5

400.61

12.5

80.61

67.28

Low Power (fCLK =

76.8 kHz)

240

2.5

401.22

12.5

81.22

67.89

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

When conversions are being performed on a single channel and

a step change occurs on the analog input, the ADC continues to

output fully settled conversions if the step change is synchronized

with the conversion process. If the step change is asynchronous,

one conversion is output from the ADC, which is not completely

settled (see Figure 84).

ANALOG

INPUT

ADC

OUTPUT

FULLY

SETTLED

fADC

Figure 84. Sinc4 Zero Latency Operation

Sequencer

The description in the Sinc4 Filter section is valid when manually

switching channels, for example, writing to the device to change

channels. When multiple channels are enabled, the on-chip se-

quencer is automatically used; the device automatically sequences

between all enabled channels. In this case, the first conversion

takes the complete settling time, as listed in Table 55. For all

subsequent conversions, the time needed for each conversion is

the settling time also, but the dead time is reduced to:

►

30 when the old channel and the new channel both have an

FS[10:0] > 1 or both have an FS[10:0] = 1.

►

−4 when the old channel has an FS[10:0] > 1 and the new

channel has an FS[10:0] = 1.

►

64 when the old channel has an FS[10:0] = 1 and the new

channel has an FS[10:0] > 1.

Sinc4 50 Hz and 60 Hz Rejection

Figure 85 shows the frequency response of the sinc4 filter when

the output data rate is programmed to 50 SPS and zero latency is

disabled. For the same configuration but with zero latency enabled,

the filter response remains the same but the output data rate is 12.5

SPS. The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of

120 dB minimum, assuming a stable controller clock.

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