ADFS7124-8BBCPZ datasheet(48/93 Pages) AD

48 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 48 of 93

AVDD = 3 V. If the ADC is configured for bipolar mode, the analog

input range on the AINP input is 0 V to AVDD. The bipolar/unipolar

option is chosen by programming the bipolar bit in the configuration

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input voltage

resulting in a code of 00 … 00, a midscale voltage resulting in a

code of 100 … 000, and a full-scale input voltage resulting in a

code of 111 … 111. The output code for any analog input voltage

can be represented as

Code = (2N × AIN × Gain)/VREF

When the ADC is configured for bipolar operation, the output code

is offset binary with a negative full-scale voltage resulting in a code

of 000 … 000, a zero differential input voltage resulting in a code

of 100 … 000, and a positive full-scale input voltage resulting in a

code of 111 … 111. The output code for any analog input voltage

can be represented as

Code = 2N − 1 × [(AIN × Gain/VREF) + 1]

where:

N = 24.

AIN is the analog input voltage.

Gain is the gain setting (1 to 128).

EXCITATION CURRENTS

The ADFS7124-8 also contains two matched, software configura-

ble, constant current sources that can be programmed to equal

0.1 µA, 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, or 1 mA. These

current sources can be used to excite external resistive bridges or

RTD sensors. Both current sources source currents from AVDD and

can be directed to any of the analog input pins (see Figure 77).

The pins on which the currents are made available are programmed

using the IOUT1_CH and IOUT0_CH bits in the IO_CONTROL_1

individually programmable using the IOUT1 and IOUT0 bits in the

IO_CONTROL_1 register. In addition, both currents can be output

to the same analog input pin.

Note that the on-chip reference does not need to be enabled when

using the excitation currents.

AIN0

AIN1

AVDD

VBIAS

IOUT1

IOUT0

AVDD

AVSS

AVDD

AVSS

AIN15

AVDD

AVSS

VBIAS

PGA

TO ADC

BURNOUT

CURRENTS

Figure 77. Excitation Current and Bias Voltage Connections

BRIDGE POWER-DOWN SWITCH

In bridge applications such as strain gages and load cells, the

bridge itself consumes the majority of the current in the system. For

example, a 350 Ω load cell requires 8.6 mA of current when excited

with a 3 V supply. To minimize the current consumption of the

system, the bridge can be disconnected (when it is not being used)

using the bridge power-down switch. The switch can withstand 30

mA of continuous current, and it has an on-resistance of 10 Ω

maximum. The PDSW bit in the IO_CONTROL_1 register controls

the switch.

LOGIC OUTPUTS

The ADFS7124-8 has four general-purpose digital outputs: P1

to P4. These are enabled using the GPIO_CTRL bits in the

IO_CONTROL_1 register (see Table 50). The pins can be pulled

high or low using the GPIO_DATx bits in the register; that is, the

value at the pin is determined by the setting of the GPIO_DATx bits.

The logic levels for these pins are determined by AVDD rather than

by IOVDD.

Table 50. Input/Output Control 1 Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x03

IO_

CONTROL

[23:16] GPIO_DAT4 GPIO_DAT3 GPIO_DAT2 GPIO_DAT1 GPIO_CTRL

GPIO_CTRL

0x000000 RW

[15:8]

PDSW

IOUT1

IOUT0

[7:0]

IOUT1_CH

IOUT0_CH

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