ADFS7124-8BBCPZ datasheet(7/93 Pages) AD

7 / 93 page

Data Sheet

ADFS7124-8

SPECIFICATIONS

analog.com

Rev. 0 | 7 of 93

Table 2. Specifications (Continued)

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

Common-Mode Rejection

100

EXCITATION CURRENT SOURCES (IOUT0/IOUT1)

Available on any analog input pin

Output Current

0.1/50/100/250/

500/750/1000

µA

Initial Tolerance

±4

TA = 25°C

Drift

ppm/°C

Current Matching

±0.5

Matching between IOUT0 and IOUT1, VOUT

= 0 V

Drift Matching2

ppm/°C

Line Regulation (AVDD)

%/V

AVDD = 3 V ± 5%

Load Regulation

0.2

%/V

Output Compliance2

AVSS − 0.05

AVDD − 0.37

50 µA/100 µA/250 µA/500 µA current

sources, 2% accuracy

AVSS − 0.05

AVDD − 0.48

750 µA and 1000 µA current sources, 2%

accuracy

BIAS VOLTAGE (VBIAS) GENERATOR

Available on any analog input pin

VBIAS

AVSS + (AVDD −

AVSS)/2

VBIAS Generator Start-Up Time

6.7

µs/nF

Dependent on the capacitance connected

to AINx

TEMPERATURE SENSOR

Accuracy

±0.5

°C

Sensitivity

13,584

codes/°C

LOW-SIDE POWER SWITCH

On Resistance (RON)

Ω

Allowable Current2

Continuous current

BURNOUT CURRENTS

AIN Current

0.5/2/4

µA

Analog inputs must be buffered

DIGITAL OUTPUTS (P1 to P4)

Output Voltage

High, VOH

AVDD − 0.6

ISOURCE = 100 µA

Low, VOL

0.4

ISINK = 100 µA

DIAGNOSTICS

Power Supply Monitor Detect Level

Analog Low Dropout Regulator (ALDO)

1.6

AVDD − AVSS ≥ 2.7 V

Digital LDO (DLDO)

1.55

IOVDD ≥ 1.75 V

Reference Detect Level

0.7

REF_DET_ERR bit active if VREF < 0.7 V

AINM/AINP Overvoltage Detect Level

AVDD + 0.04

AINM/AINP Undervoltage Detect Level

AVSS − 0.04

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency

614.4 − 5%

614.4

614.4 + 5%

kHz

Duty Cycle

50:50

External Clock

Frequency

2.4576

MHz

Internal divide by 4

Duty Cycle Range

45:55 to 55:45

LOGIC INPUTS2

Input Voltage

Low, VINL

0.3 × IOVDD

1.65 V ≤ IOVDD < 1.9 V

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