ADFS7124-8BBCPZ datasheet(81/93 Pages) AD

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Data Sheet

ADFS7124-8

ON-CHIP REGISTERS

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Rev. 0 | 81 of 93

Table 65. Status Register Bit Descriptions (Continued)

Bits

Bit Name

Description

data. It is also set when the device is placed in the power-down or standby mode. The end of a conversion is also indicated by the

DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data.

ERROR_FLAG

ADC error bit. This bit indicates if one of the error bits is asserted in the error register. This bit is high if one or more of the error bits in the

error register is set. This bit is cleared by a read of the error register.

This bit is set to 0.

POR_FLAG

Power-on reset flag. This bit indicates that a power-on reset occurred. A power-on reset occurs on power-up, when the power supply

voltage goes below a threshold voltage, when a reset is performed, and when coming out of power-down mode. The status register must be

read to clear the bit.

3:0

CH_ACTIVE

These bits indicate which channel is being converted by the ADC.

0000 = Channel 0.

0001 = Channel 1.

0010 = Channel 2.

0011 = Channel 3.

0100 = Channel 4.

0101 = Channel 5.

0110 = Channel 6.

0111 = Channel 7.

1000 = Channel 8.

1001 = Channel 9.

1010 = Channel 10.

1011 = Channel 11.

1100 = Channel 12.

1101 = Channel 13.

1110 = Channel 14.

1111 = Channel 15.

ADC_CONTROL REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 1

Power-On/Reset = 0x0000

Table 66 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (0)

DOUT_RDY_DEL (0)

CONT_READ (0)

DATA_STATUS (0)

CS_EN (0)

REF_EN (0)

POWER_MODE (0)

Mode (0)

CLK_SEL (0)

Table 66. ADC Control Register Bit Descriptions

Bits

Bit Name

Description

15:13

These bits must be programmed with a Logic 0 for correct operation.

DOUT_RDY_DEL

Controls the SCLK inactive edge to DOUT/RDY high time. When DOUT_RDY_DEL is cleared, the delay is 10 ns minimum. When

DOUT_RDY_DEL is set, the delay is increased to 100 ns minimum. This function is useful when CS is tied low (the CS_EN bit is

set to 0).

CONT_READ

Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured

so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT

pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications

register does not have to be written to for subsequent data reads. To enable continuous read, the CONT_READ bit is set. To

disable continuous read, write a read data command while the DOUT/ RDY pin is low. While continuous read is enabled, the ADC

monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 64

consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to the device.

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